Intel BX80613I7980 Datasheet Download Page 33

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Datasheet, Volume 1

Electrical Specifications

Table 2-18. Parameter Values for Intel

QuickPath Interconnect (Intel

QPI) Channel at

6.4 GT/s

Notes:

1. It is expected that the receiver will have equalization, which will boost received voltage and mitigate timing jitter, with the

minimum level of swing specified. Platform electrical design should determine the optimum level of equalization necessary,

depending on the link.

Symbol

Parameter

Min

Nom

Max

Unit

Notes

TX_LOW_CM_DC

DC resistance of Tx terminations at half the

single ended swing (which is usually 0.25*V

Tx-

diff-pp-pin

) bias point

—

ohms

RX_LOW_CM_DC

DC resistance of Rx terminations at half the

single ended swing (which is usually 0.25*V

Tx-

diff-pp-pin

) bias point

—

ohms

Tx-diff-pp-pin

Transmitter Differential swing

800

—

1400

Tx-cm-dc-pin

Transmitter output DC common mode, defined as

average of V

D+

and V

D-

0.23

—

Fraction of

TX-diff-pp-pin

Tx-cm-ac-pin

Transmitter output AC common mode, defined as

((V

D+

+ V

D–

)/2 – V

TX-cm-dc-pin

–0.0375

—

0.0375

Fraction of

TX-diff-pp-pin

duty-pin

Average of UI-UI jitter

-0.05

—

0.05

jitUI-UI-1E-7pin

UI-UI jitter measured at Tx output pins with 1E-7

probability

-0.07

—

0.07

jitUI-UI-1E-9pin

UI-UI jitter measured at Tx output pins with 1E-9

probability

-0.075

—

0.075

clk-acc-jit-N_UI-1E-7

P-p accumulated jitter out of any Tx data or clock

over 0



N UI where N=12, measured with

1E-7 probability.

—

0.18

clk-acc-jit-N_UI-1E-9

P-p accumulated jitter out of any Tx data or clock

over 0



N UI where N=12, measured with 1E-

9 probability.

—

0.2

Tx-data-clk-skew-pin

Delay of any data lane relative to clock lane, as

measured at Tx output (UI)

-0.5

—

0.5

Rx-data-clk-skew-pin

Delay of any data lane relative to the clock lane,

as measured at the end of Tx+Channel. This

parameter is a collective sum of effects of data

clock mismatches in Tx and on the medium

connecting Tx and Rx. (UI).

-1

—

Rx-cm-dc-pin

DC common mode ranges at the Rx input for any

data or clock channel, defined as average of V

D+

and V

D-

(mV)

—

350

Rx-cm-ac-pin

AC common mode ranges at the Rx input for any

data or clock channel, defined as ((VD+ + VD-)/2

– VRX-cm-dc-pin).

–50

—

Rx-margin

Measured timing margin during receiver

margining with any receiver equalizer off

0.1

—

Rx-margin

Measured voltage margin during receiver

margining with receiver equalizer off

—

Rx-margin-RxEQ

Measured timing margin during receiver

margining with receiver equalizer on and at the

optimum setting that maximizes the timing

margin

0.12

—

Rx-margin-RxEQ

Measured voltage margin during receiver

margining with receiver equalizer on and at the

optimum setting that maximizes the voltage

margin

—

Summary of Contents for BX80613I7980

Page 1: ...Document 323252 003 Intel Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series on 32 nm Process Datasheet Volume 1 June 2011...

Page 2: ...BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www i...

Page 3: ...ltage Validation 31 2 12 Intel QuickPath Interconnect Intel QPI Specifications 32 3 Package Mechanical Specifications 35 3 1 Package Mechanical Drawing 35 3 2 Processor Component Keep Out Zones 38 3 3...

Page 4: ...State 90 7 2 1 2 C1 C1E State 90 7 2 1 3 C3 State 91 7 2 1 4 C6 State 91 7 2 2 Package Power State Descriptions 91 7 2 2 1 Package C0 State 91 7 2 2 2 Package C1 C1E State 91 7 2 2 3 Package C3 State...

Page 5: ...mal Profile 77 6 2 Intel Core i7 900 Desktop Processor Series Thermal Profile 78 6 3 Thermal Test Vehicle TTV Case Temperature TCASE Measurement Location 80 6 4 Frequency and Voltage Ordering 82 7 1 P...

Page 6: ...tel QuickPath Interconnect Intel QPI Specifications 32 2 18 Parameter Values for Intel QuickPath Interconnect Intel QPI Channel at 6 4 GT s 33 3 1 Processor Loading Specifications 38 3 2 Package Handl...

Page 7: ...vision Number Description Date 001 Initial release March 2010 002 Added Intel Core i7 970 desktop processor series July 2010 003 Added Intel Core i7 990X desktop processor Extreme Edition Added Intel...

Page 8: ...8 Datasheet Volume 1...

Page 9: ...e referred to as the processor Note The Intel Core i7 900 desktop processor Extreme Edition series on 32 nm process refers to the Intel Core i7 980X and i7 990X desktop processor Extreme Edition Note...

Page 10: ...DDR memory standard that is being developed as the successor to DDR2 SRDRAM Intel QuickPath Interconnect Intel QPI Intel QPI is a cache coherent point to point link based electrical interconnect speci...

Page 11: ...terial and concepts available in the following documents may be beneficial when reading this document Notes 1 Contact your Intel representative to receive the latest revisions of these documents 2 Doc...

Page 12: ...Introduction 12 Datasheet Volume 1...

Page 13: ...rocessor has 210 VCC pads and 119 VSS pads associated with VCC 8 VTTA pads and 5 VSS pads associated with VTTA 28 VTTD pads and 17 VSS pads associated with VTTD 28 VDDQ pads and 17 VSS pads associated...

Page 14: ...Intel QPI link frequency such as no core frequency to Intel QPI multiplier The processor maximum core frequency Intel QPI link frequency and integrated memory controller frequency are set during manu...

Page 15: ...ection of voltages Table 2 1 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor s...

Page 16: ...1 0 0 92500 0 0 0 1 0 1 0 0 1 48750 0 1 1 0 1 1 1 1 0 91875 0 0 0 1 0 1 0 1 1 48125 0 1 1 1 0 0 0 0 0 91250 0 0 0 1 0 1 1 0 1 47500 0 1 1 1 0 0 0 1 0 90625 0 0 0 1 0 1 1 1 1 46875 0 1 1 1 0 0 1 0 0 9...

Page 17: ...1 18750 1 0 0 1 1 1 1 1 0 61875 0 1 0 0 0 1 0 1 1 18125 1 0 1 0 0 0 0 0 0 61250 0 1 0 0 0 1 1 0 1 17500 1 0 1 0 0 0 0 1 0 60625 0 1 0 0 0 1 1 1 1 16875 1 0 1 0 0 0 1 0 0 60000 0 1 0 0 1 0 0 0 1 16250...

Page 18: ...connected through a resistor to ground VSS Unused outputs may be left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary sca...

Page 19: ...R3 Reference Clocks Differential DDR3 Output DDR 0 1 2 _CLK D P 3 0 DDR3 Command Signals Single ended CMOS Output DDR 0 1 2 _RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 _MA 15 0 DDR 0 1 2 _BA 2 0 Singl...

Page 20: ...Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other component...

Page 21: ...specifications shown in Table 2 5 is used with devices normally operating from a VTTD interface supply VTTD nominal levels will vary between processor families All PECI devices will operate at the VTT...

Page 22: ...subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceedi...

Page 23: ...deband and Test Access Port TAP are listed in Table 2 12 through Table 2 15 Table 2 7 through Table 2 15 list the DC specifications for the processor and are valid only while meeting specifications fo...

Page 24: ...n 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Refer to Table 2 8 and Figure 2 3 for the minimum typical and maximum VCC allowed for a given current The proc...

Page 25: ...0 031 VID 0 050 1 2 3 20 VID 0 016 VID 0 035 VID 0 054 1 2 3 25 VID 0 020 VID 0 039 VID 0 058 1 2 3 30 VID 0 024 VID 0 043 VID 0 062 1 2 3 35 VID 0 028 VID 0 047 VID 0 066 1 2 3 40 VID 0 032 VID 0 05...

Page 26: ...e 2 9 VTT Voltage Identification VID Definition VTT VR VID Input VTT_Typ VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 1 0 0 0 0 1 0 1 220 V 0 1 0 0 0 1 1 0 1 195 V 0 1 0 0 1 0 1 0 1 170 V 0 1 0 0 1 1 1 0...

Page 27: ...D 0 0615 6 VID 0 0045 VID 0 0360 VID 0 0675 7 VID 0 0105 VID 0 0420 VID 0 0735 8 VID 0 0165 VID 0 0480 VID 0 0795 9 VID 0 0225 VID 0 0540 VID 0 0855 10 VID 0 0285 VID 0 0600 VID 0 0915 11 VID 0 0345 V...

Page 28: ...DQ 2 RON RON RVTT_TERM V VOH Output High Voltage VDDQ VDDQ 2 RON RON RVTT_TERM V 4 RON DDR3 Clock Buffer On Resistance 21 31 7 RON DDR3 Command Buffer On Resistance 16 24 RON DDR3 Reset Buffer On Resi...

Page 29: ...river is tristated 4 VIH and VOH may experience excursions above VTT Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The VTTA referred to in these...

Page 30: ...stance must be provided on the system board with 1 resistors COMP0 resistors are to VSS Table 2 14 PWRGOOD Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltag...

Page 31: ...e voltage VCC overshoot events at the processor must meet the specifications in Table 2 16 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are 10 ns in duration may be ign...

Page 32: ...idated 1 000 000 ZTX_HIGH_CM_DC Single ended DC impedance to GND for either D or D of any data bit at Tx 10 k 1 Notes 1 Indicates the output impedance of the transmitter during initialization when the...

Page 33: ...ins with 1E 9 probability 0 075 0 075 UI TXclk acc jit N_UI 1E 7 P p accumulated jitter out of any Tx data or clock over 0 n N UI where N 12 measured with 1E 7 probability 0 0 18 UI TXclk acc jit N_UI...

Page 34: ...Electrical Specifications 34 Datasheet Volume 1...

Page 35: ...HS Thermal Interface Material TIM Processor core die Package substrate Capacitors Note 1 Socket and motherboard are included for reference and are not part of the processor package 3 1 Package Mechani...

Page 36: ...T 1 OF 2 FINISH MATERIAL DATE APPROVED BY DATE CHECKED BY DATE DRAWN BY DATE DESIGNED BY UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14 5M 1994 DIMENSIONS A...

Page 37: ...ONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION D76126 2 7 DWG NO SHT REV DEPARTMENT 2200 MISSION COLLEGE BLVD P...

Page 38: ...oading in a direction normal to the processor IHS 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor inter...

Page 39: ...he package components and associated materials 3 8 Processor Markings Figure 3 4 shows the top side markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Pr...

Page 40: ...olume 1 3 9 Processor Land Coordinates Figure 3 5 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Pr...

Page 41: ...E19 CLOCK O DDR0_CLK_P 0 J19 CLOCK O DDR0_CLK_P 1 D19 CLOCK O DDR0_CLK_P 2 F18 CLOCK O DDR0_CLK_P 3 E20 CLOCK O DDR0_CS 0 G15 CMOS O DDR0_CS 1 B10 CMOS O DDR0_CS 4 B15 CMOS O DDR0_CS 5 A7 CMOS O DDR0...

Page 42: ...A 11 A26 CMOS O DDR0_MA 12 B26 CMOS O DDR0_MA 13 A10 CMOS O Table 4 1 Land Listing by Land Name Sheet 3 of 29 Land Name Land No Buffer Type Direction DDR0_MA 14 A28 CMOS O DDR0_MA 15 B29 CMOS O DDR0_M...

Page 43: ...DQ 57 W7 CMOS I O DDR1_DQ 58 Y10 CMOS I O Table 4 1 Land Listing by Land Name Sheet 5 of 29 Land Name Land No Buffer Type Direction DDR1_DQ 59 W10 CMOS I O DDR1_DQ 60 V9 CMOS I O DDR1_DQ 61 W5 CMOS I...

Page 44: ...38 CMOS I O Table 4 1 Land Listing by Land Name Sheet 7 of 29 Land Name Land No Buffer Type Direction DDR2_DQ 32 K12 CMOS I O DDR2_DQ 33 J12 CMOS I O DDR2_DQ 34 H13 CMOS I O DDR2_DQ 35 L13 CMOS I O DD...

Page 45: ...9 of 29 Land Name Land No Buffer Type Direction QPI_DRX_DN 13 AN42 QPI I QPI_DRX_DN 14 AM43 QPI I QPI_DRX_DN 15 AM40 QPI I QPI_DRX_DN 16 AM41 QPI I QPI_DRX_DN 17 AP40 QPI I QPI_DRX_DN 18 AP39 QPI I Q...

Page 46: ...SVD A37 RSVD B34 RSVD C34 RSVD G34 RSVD G33 RSVD D36 RSVD F36 RSVD E33 RSVD G36 RSVD E37 RSVD F37 RSVD E34 RSVD G35 RSVD G30 RSVD G29 RSVD H32 RSVD F33 RSVD E29 RSVD E30 RSVD J31 RSVD J30 Table 4 1 La...

Page 47: ...D5 RSVD AD6 RSVD AD7 Table 4 1 Land Listing by Land Name Sheet 13 of 29 Land Name Land No Buffer Type Direction RSVD AD8 RSVD AE1 RSVD AE3 RSVD AE4 RSVD AE5 RSVD AE6 RSVD AF1 RSVD AF2 RSVD AF3 RSVD AF...

Page 48: ...ble 4 1 Land Listing by Land Name Sheet 15 of 29 Land Name Land No Buffer Type Direction RSVD AW41 RSVD AW42 RSVD AW5 RSVD AW7 RSVD AY3 RSVD AY35 RSVD AY39 RSVD AY4 RSVD AY40 RSVD AY41 RSVD AY5 RSVD A...

Page 49: ...VCC AN12 PWR VCC AN13 PWR Table 4 1 Land Listing by Land Name Sheet 17 of 29 Land Name Land No Buffer Type Direction VCC AN15 PWR VCC AN16 PWR VCC AN18 PWR VCC AN19 PWR VCC AN21 PWR VCC AN24 PWR VCC...

Page 50: ...WR VCC AV9 PWR VCC AW10 PWR Table 4 1 Land Listing by Land Name Sheet 19 of 29 Land Name Land No Buffer Type Direction VCC AW12 PWR VCC AW13 PWR VCC AW15 PWR VCC AW16 PWR VCC AW18 PWR VCC AW19 PWR VCC...

Page 51: ...Table 4 1 Land Listing by Land Name Sheet 21 of 29 Land Name Land No Buffer Type Direction VDDQ F24 PWR VDDQ G17 PWR VDDQ G22 PWR VDDQ G27 PWR VDDQ H15 PWR VDDQ H20 PWR VDDQ H25 PWR VDDQ J18 PWR VDDQ...

Page 52: ...S AL26 GND VSS AL29 GND Table 4 1 Land Listing by Land Name Sheet 23 of 29 Land Name Land No Buffer Type Direction VSS AL32 GND VSS AL35 GND VSS AL36 GND VSS AL37 GND VSS AL42 GND VSS AL7 GND VSS AM11...

Page 53: ...ND VSS AV17 GND VSS AV20 GND Table 4 1 Land Listing by Land Name Sheet 25 of 29 Land Name Land No Buffer Type Direction VSS AV22 GND VSS AV23 GND VSS AV26 GND VSS AV29 GND VSS AV32 GND VSS AV39 GND VS...

Page 54: ...ND VSS M14 GND VSS M16 GND Table 4 1 Land Listing by Land Name Sheet 27 of 29 Land Name Land No Buffer Type Direction VSS M18 GND VSS M2 GND VSS M20 GND VSS M22 GND VSS M24 GND VSS M26 GND VSS M28 GND...

Page 55: ...R VTTD AA10 PWR VTTD AA11 PWR VTTD AA33 PWR VTTD AB10 PWR VTTD AB11 PWR VTTD AB33 PWR VTTD AB34 PWR VTTD AB8 PWR VTTD AB9 PWR VTTD AC10 PWR VTTD AC11 PWR VTTD AC33 PWR VTTD AC34 PWR VTTD AC35 PWR VTTD...

Page 56: ...2 CMOS O B12 VDDQ PWR B13 DDR0_WE CMOS O B14 DDR1_MA 13 CMOS O B15 DDR0_CS 4 CMOS O B16 DDR0_BA 0 CMOS O B17 VDDQ PWR B18 RSVD B19 DDR0_MA 10 CMOS O B20 RSVD B21 DDR0_MA 1 CMOS O B22 VDDQ PWR B23 DDR...

Page 57: ...1 BPM 4 GTL I O Table 4 2 Land Listing by Land Number Sheet 3 of 29 Land No Pin Name Buffer Type Direction D2 BPM 6 GTL I O D3 VSS GND D4 RSVD D5 RSVD D6 DDR1_DQ 38 CMOS I O D7 DDR1_DQS_N 4 CMOS I O D...

Page 58: ...I O F11 DDR1_ODT 3 CMOS O Table 4 2 Land Listing by Land Number Sheet 5 of 29 Land No Pin Name Buffer Type Direction F12 DDR0_ODT 0 CMOS O F13 DDR2_ODT 1 CMOS O F14 VDDQ PWR F15 DDR2_MA 13 CMOS O F16...

Page 59: ...CLK_P 2 CLOCK O Table 4 2 Land Listing by Land Number Sheet 7 of 29 Land No Pin Name Buffer Type Direction H22 DDR2_MA 9 CMOS O H23 DDR2_MA 11 CMOS O H24 DDR2_MA 14 CMOS O H25 VDDQ PWR H26 DDR1_MA 14...

Page 60: ...umber Sheet 9 of 29 Land No Pin Name Buffer Type Direction K32 DDR1_DQ 26 CMOS I O K33 RSVD K34 RSVD K35 DDR1_DQ 18 CMOS I O K36 VSS GND K37 RSVD K38 DDR2_DQ 23 CMOS I O K39 DDR2_DQS_N 2 CMOS I O K40...

Page 61: ...by Land Number Sheet 11 of 29 Land No Pin Name Buffer Type Direction M42 VSS GND M43 RSVD N1 DDR0_DQ 48 CMOS I O N2 DDR0_DQ 49 CMOS I O N3 DDR0_DQ 53 CMOS I O N4 RSVD N5 VSS GND N6 DDR2_DQ 49 CMOS I...

Page 62: ...Q 61 CMOS I O U4 DDR0_DQ 56 CMOS I O U5 DDR2_DQ 56 CMOS I O U6 DDR2_DQ 57 CMOS I O Table 4 2 Land Listing by Land Number Sheet 13 of 29 Land No Pin Name Buffer Type Direction U7 VSS GND U8 DDR2_DQS_P...

Page 63: ...WR AA34 VSS GND AA35 DDR1_DQ 4 CMOS I O AA36 DDR1_DQ 1 CMOS I O AA37 DDR1_DQ 0 CMOS I O AA38 VSS GND AA39 VSS GND Table 4 2 Land Listing by Land Number Sheet 15 of 29 Land No Pin Name Buffer Type Dire...

Page 64: ...RSVD AF5 VSS GND AF6 RSVD Table 4 2 Land Listing by Land Number Sheet 17 of 29 Land No Pin Name Buffer Type Direction AF7 VTT_VID3 CMOS O AF8 VTTD PWR AF9 VTTD PWR AF33 VTTA PWR AF34 VTTA PWR AF35 VSS...

Page 65: ...R AK14 VSS GND AK15 VCC PWR AK16 VCC PWR Table 4 2 Land Listing by Land Number Sheet 19 of 29 Land No Pin Name Buffer Type Direction AK17 VSS GND AK18 VCC PWR AK19 VCC PWR AK20 VSS GND AK21 VCC PWR AK...

Page 66: ...e 4 2 Land Listing by Land Number Sheet 21 of 29 Land No Pin Name Buffer Type Direction AM27 VCC PWR AM28 VCC PWR AM29 VSS GND AM30 VCC PWR AM31 VCC PWR AM32 VSS GND AM33 VCC PWR AM34 VCC PWR AM35 VSS...

Page 67: ...able 4 2 Land Listing by Land Number Sheet 23 of 29 Land No Pin Name Buffer Type Direction AP37 VSS GND AP38 QPI_DRX_DP 19 QPI I AP39 QPI_DRX_DN 18 QPI I AP40 QPI_DRX_DN 17 QPI I AP41 QPI_DRX_DP 17 QP...

Page 68: ...VSS GND AU2 RSVD AU3 RSVD Table 4 2 Land Listing by Land Number Sheet 25 of 29 Land No Pin Name Buffer Type Direction AU4 RSVD AU5 VSS GND AU6 RSVD AU7 RSVD AU8 RSVD AU9 VCC PWR AU10 VCC PWR AU11 VSS...

Page 69: ...W12 VCC PWR AW13 VCC PWR Table 4 2 Land Listing by Land Number Sheet 27 of 29 Land No Pin Name Buffer Type Direction AW14 VSS GND AW15 VCC PWR AW16 VCC PWR AW17 VSS GND AW18 VCC PWR AW19 VCC PWR AW20...

Page 70: ...D AY27 VCC PWR AY28 VCC PWR AY29 VSS GND AY30 VCC PWR AY31 VCC PWR AY32 VSS GND AY33 VCC PWR AY34 VCC PWR AY35 RSVD AY36 QPI_DRX_DN 3 QPI I AY37 VSS GND AY38 QPI_DRX_DN 6 QPI I AY39 RSVD AY40 RSVD AY4...

Page 71: ...0 I Must be terminated on the system board using a precision resistor QPI_DRX_DN 19 0 QPI_DRX_DP 19 0 I I QPI_DRX_DN 19 0 and QPI_DRX_DP 19 0 comprise the differential receive data for the QPI port T...

Page 72: ...signal can also be driven to the processor to activate the Thermal Control Circuit This signal does not have on die termination and must be terminated on the system board PSI O Processor Power Status...

Page 73: ...set VCC I Power for processor core VCC_SENSE VSS_SENSE O O VCC_SENSE and VSS_SENSE provide an isolated low impedance connection to the processor core power and ground They can be used to sense or meas...

Page 74: ...C 2 0 Current Sense Configuration bits for ISENSE gain setting See Voltage Regulator Down VRD 11 1 Design Guidelines for gain setting information This value is latched on the rising edge of VTTPWRGOOD...

Page 75: ...rmal solution that was verified compliant to the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update No redesign of the...

Page 76: ...ermal and Mechanical Design Guidelines see Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Notes 1 These values are specified at VCC_MAX for...

Page 77: ...Tcase in C y 43 2 0 19 P Table 6 2 Intel Core i7 900 Desktop Processor Extreme Edition Series Thermal Profile Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C 0 43 2 34...

Page 78: ...Processor Series Thermal Profile Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C 0 44 1 34 50 6 68 57 0 100 63 1 2 44 5 36 50 9 70 57 4 102 63 5 4 44 9 38 51 3 72 57 8...

Page 79: ...uidelines see Section 1 2 for details on characterizing the fan speed to CA and ambient temperature measurement Notes 1 The ambient temperature is measured at the inlet to the processor thermal soluti...

Page 80: ...t methodology and attaching the thermocouple refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Notes 1 Figure is not to scale and is for reference only 2 B1 M...

Page 81: ...telligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperature a...

Page 82: ...still 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and Frequency VID reduction will continue until either the mini...

Page 83: ...activation temperature TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio VID state 6 2 2 4 Critical Temperature Flag If TM2 is unable to reduce the processor tem...

Page 84: ...tomatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 THERMTRIP activation is independent of processor activity The temperature at w...

Page 85: ...lliseconds over which the DTS temperature values are averaged Short averaging times will make the averaged temperature values respond more quickly to DTS changes Long averaging times will result in be...

Page 86: ...the time frame when reliable data is not available using PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the host controller should take acti...

Page 87: ...Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 2 These ratings apply to the Intel...

Page 88: ...Thermal Specifications 88 Datasheet Volume 1...

Page 89: ...ate requests inside the processor and do not directly result in I O reads to the system The P_LVLx I O Monitor address does not need to be set up before using the P_LVLx I O read interface Software ma...

Page 90: ...processor to initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the C1 state See the Intel 64 and IA 32 Architecture Software Developer s Manua...

Page 91: ...1 Package C0 State This is the normal operating state for the processor The processor remains in the Normal state when at least one of its cores is in the C0 or C1 state or when another component in t...

Page 92: ...ocessor itself will never request a particular S state Notes 1 If the chipset requests an S state transition which is not allowed a machine check error will be generated by the processor 7 4 ACPI P St...

Page 93: ...in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the VCC i...

Page 94: ...Features 94 Datasheet Volume 1...

Page 95: ...hapter are dimensioned in millimeters and inches in brackets Figure 8 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Inte...

Page 96: ...heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8 2 side view and Figure...

Page 97: ...Notes 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 8 3 Space Requirements for the Boxed Processor top view Figure 8 4 Sp...

Page 98: ...al that is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if a...

Page 99: ...into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink...

Page 100: ...Processor Specifications 100 Datasheet Volume 1 Figure 8 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements top view Figure 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements sid...

Page 101: ...rnal chassis temperature should be kept below 40 C Meeting the processor s temperature specification see Chapter 6 is the responsibility of the system integrator The motherboard must supply a constant...

Page 102: ...more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sen...

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