Intel BX80605I5760 Specification Download Page 1

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Reference Number:

322166-015

Intel

Core

i7-800 and i5-700

Desktop Processor Series

Specification Update

March 2011

Summary of Contents for BX80605I5760

Page 1: ...Reference Number 322166 015 Intel CoreTM i7 800 and i5 700 Desktop Processor Series Specification Update March 2011...

Page 2: ...a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Intel Trusted Ex...

Page 3: ...Specification Update Contents Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 14 Errata 17 Specification Changes 53 Specification Clarifications 54 Documentation C...

Page 4: ...Contents 4 Specification Update...

Page 5: ...Added Errata AAN111 and AAN112 February 2010 008 Added Erratum AAN113 March 2010 009 Added Errata AAN114 and AAN115 April 2010 010 Updated Processor Identification table to include the Intel Core i7...

Page 6: ...t Volume 2 322165 001 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32...

Page 7: ...f the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be inc...

Page 8: ...Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification c...

Page 9: ...es May be Preempted AAN13 X No Fix General Protection GP Fault May Not Be Signaled on Data Segment Limit Violation above 4 G Limit AAN14 X No Fix LBR BTS BTM May Report a Wrong Address when an Excepti...

Page 10: ...o Fix Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 AAN41 X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur AAN42 X No F...

Page 11: ...RETIRED and MEM_INST_RETIRED May Count Inaccurately AAN67 X No Fix A Page Fault May Not be Generated When the PS bit is set to 1 in a PML4E or PDPTE AAN68 X No Fix CPURESET Bit Does Not Get Cleared AA...

Page 12: ...Possible on Overflow of Fixed Counter 0 AAN94 X No Fix SVID and SID of Devices 8 and 16 only implement bits 7 0 AAN95 X No Fix No_Soft_Reset Bit in the PMCSR Does Not Operate as Expected AAN96 X No Fi...

Page 13: ...ts for Hardware Prefetches Which Miss The L1 Data Cache May be Over Counted AAN120 X No Fix VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL 34 32 AAN121 X No Fix PCIe Port s LTSSM May Not Transiti...

Page 14: ...field of the Device ID register accessible through Boundary Scan 6 The Stepping ID in bits 3 0 indicates the revision number of that model See Table 1 for the processor stepping ID number in the CPUID...

Page 15: ...z 2 Shared L3 Cache Size MB Notes 9 SLBPS i7 880 B 1 106E5h 3 06 1333 4 core 3 33 3 core 3 33 2 core 3 60 1 core 3 73 8 1 3 4 5 6 SLBS2 i7 875K B 1 106E5h 2 93 1333 4 core 3 20 3 core 3 20 2 core 3 46...

Page 16: ...lization Technology Intel Virtualization Technology Intel VT x and Intel Virtualization Technology for Directed I O Intel VT d 8 This processor has TDP of 82W and meets the 1156_VR_CONF_09A VR Configu...

Page 17: ...ations in Pentium 4 Intel Xeon and P6 Family Processors the processor performs REP MOVS or REP STOS as fast strings Due to this erratum fast string REP MOVS REP STOS instructions that cross page bound...

Page 18: ...pected values Implication Performance Monitoring counter SIMD_INST_RETIRED may report count higher than expected Workaround None identified Status For the steppings affected see the Summary Tables of...

Page 19: ...Summary Tables of Changes AAN7 Incorrect Address Computed For Last Byte of FXSAVE FXRSTOR Image Leads to Partial Memory Update Problem A partial memory state save of the 512 byte FXSAVE image or a pa...

Page 20: ...er s Manual Vol 1 Basic Architecture for information on the usage of the ENTER instructions This erratum is not expected to occur in ring 3 Faults are usually processed in ring 0 and stack switch occu...

Page 21: ...N14 LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode Problem An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace S...

Page 22: ...to fill occupancy counter UNC_GQ_ALLOC RT_LLC_MISS Event 02H will provide erroneous results Implication The Performance Monitoring UNC_GQ_ALLOC RT_LLC_MISS event may count a value higher than expected...

Page 23: ...of events Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAN21 GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Corr...

Page 24: ...g event signaling created by this erratum Status For the steppings affected see the Summary Tables of Changes AAN24 IA32_MPERF Counter Stops Counting During On Demand TM1 Problem According to the Inte...

Page 25: ...ion temperature and then Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR 1A0H bit 3 a subsequent re enable of Thermal Monitor will result in an artificial ceiling on the maximum core P...

Page 26: ...interrupts at the same or lower priority Workaround Any vector programmed into an LVT entry must have an ISR associated with it even if that vector was programmed as masked This ISR routine must do a...

Page 27: ...on Bits 53 50 of the IA32_VMX_BASIC MSR report that the WB write back memory type will be used but the processor may use a different memory type Workaround Software should ensure that the VMCS and ref...

Page 28: ...che line splits for optimization purposes may read excessive number of memory misalignment events Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAN38 C...

Page 29: ...that the processor thread begins a transition to a low power C state the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0 Implication Due to this erratum...

Page 30: ...eived on the same internal clock that the ESR is being written as part of the write read ESR access flow The corresponding error interrupt will also not be generated for this case Implication Due to t...

Page 31: ...monitor interrupts PMI s from Uncore fixed counters are ignored when Uncore general performance monitor counters 3B0H 3BFH are not programmed Implication This erratum blocks a usage model in which eac...

Page 32: ...s of Changes AAN51 Faulting Executions of FXRSTOR May Update State Inconsistently Problem The state updated by a faulting FXRSTOR instruction may vary from one execution to another Implication Softwar...

Page 33: ...be an interruption in the counting of a previously programmed event during the programming of a new event Workaround Before programming the performance event select registers IA32_PERFEVTSELx MSR 186H...

Page 34: ...ble to non writable without software performing an appropriate TLB invalidation When a subsequent access to that address by a specific instruction ADD AND BTC BTR BTS CMPXCHG DEC INC NEG NOT OR ROL RO...

Page 35: ...e operation is not supported on the DRAM the memory controller will not enter self refresh if software has REF_2X_NOW bit 4 of the MC_CLOSED_LOOP CSR function 3 offset 84H set This scenario may cause...

Page 36: ...ummary Tables of Changes AAN63 PSI Signal May Incorrectly be Left Asserted Problem When some of the cores in the processor are in C3 C6 state the PSI Power Status Indicator signal may incorrectly be l...

Page 37: ...ings affected see the Summary Tables of Changes AAN67 A Page Fault May Not be Generated When the PS bit is set to 1 in a PML4E or PDPTE Problem On processors supporting Intel 64 architecture the PS bi...

Page 38: ...e PCIe port However the Power State field is incorrectly modified Workaround None identified Status For the steppings affected see the Summary Tables of Changes AAN71 PECI Accesses to Registers May Fa...

Page 39: ...Tables of Changes AAN75 BIST Results May be Additionally Reported After a GETSEC WAKEUP or INIT SIPI Sequence Problem BIST results should only be reported in EAX the first time a logical processor wa...

Page 40: ...will not match the actual payload size Implication Due to this erratum malformed PCIe packets could be transmitted Workaround A BIOS code change has been identified and may be implemented as a workar...

Page 41: ...OS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AAN83 Intel VT d Receiving Two Identical Interrupt Requests May Corrupt Attributes of Re...

Page 42: ...Tables of Changes AAN87 Unexpected Interrupts May Occur on C6 Exit If Using APIC Timer to Generate Interrupts Problem If the APIC timer is being used to generate interrupts unexpected interrupts not r...

Page 43: ...n Package C6 State Problem The PECI Platform Environment Control Interface PCIConfigRd command immediately followed by a PECI GetTemp command may result in a system hang Implication When the processor...

Page 44: ...ly occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows Intel Hyper Threading Technology is enabled IA32_FIXED_CTR0 local and global controls are enabled IA32_...

Page 45: ...Commands May Silently Fail During Package C6 Exit Events Problem When PCIConfigRd or PCIConfigWr commands coincide with processor package C6 exits under the right timing conditions they may fail to e...

Page 46: ...this erratum with any commercially available software Workaround None Identified Status For the steppings affected see the Summary Tables of Changes AAN101 INVLPG Following INVEPT or INVVPID May Fail...

Page 47: ...Flags DR6 B0 B3 Flags May be Incorrect for Disabled Breakpoints Problem When a debug exception is signaled on a load that crosses cache lines with data forwarded from a store and whose corresponding b...

Page 48: ...zeroed on processor warm reset Implication When this erratum occurs the IA32_MC8_CTL2 MSR will not be zeroed by warm reset Software that expects the values to be 0 coming out of warm reset may not beh...

Page 49: ...ith any commercially available software Workaround If the FP Data Operand Pointer is used in a 64 bit operating system which may run code accessing 32 bit addresses care must be taken to ensure that n...

Page 50: ...saving restoring of x87 FPU instruction and data pointers in SMRAM by setting the SMM_SAVE_CONTROL MSR 3EH bit 0 to 1 the TR Task Register selector may be restored incorrectly on the exit from SMM Imp...

Page 51: ...o to the proper state Implication PCIe Port s LTSMM may not transition according to PCIe Base Specification as described above This problem has not been seen in real system testing but was discovered...

Page 52: ...ound for this erratum Status For the steppings affected see the Summary Tables of Changes AAN126 QPI Lane May Be Dropped During Full Frequency Deskew Phase of Training Problem A random QPI Lane may be...

Page 53: ...cture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set...

Page 54: ...c Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instru...

Page 55: ...d IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation C...

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