IA-32 Intel® Architecture Optimization
E-2
N
inst
is the number of instructions in the scope of one loop
iteration.
Consider the following example of a heuristic equation assuming that
parameters have the values as indicated:
where 60 corresponds to
Nlookup
, 25 to
Nxfer
, and 1.5 to
CPI
.
The values of the parameters in the equation can be derived from the
documentation for memory components and chipsets as well as from
vendor datasheets.
Mathematical Model for PSD
The parameters used in the mathematics discussed are as follows:
psd
prefetch scheduling distance (measured in number of
iterations)
il
iteration latency
T
c
computation latency per iteration with prefetch caches
T
l
memory leadoff latency including cache miss latency,
chip set latency, bus arbitration, etc.
CAUTION.
The values in this example are for
illustration only and do not represent the actual values
for these parameters. The example is provided as a
“starting point approximation” of calculating the
prefetch scheduling distance using the above formula.
Experimenting with the instruction around the
“starting point approximation” may be required to
achieve the best possible performance
.
psd
60
25
N
pref
N
st
+
(
)
⋅
+
1.5
N
inst
⋅
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Summary of Contents for ARCHITECTURE IA-32
Page 1: ...IA 32 Intel Architecture Optimization Reference Manual Order Number 248966 013US April 2006...
Page 220: ...IA 32 Intel Architecture Optimization 3 40...
Page 434: ...IA 32 Intel Architecture Optimization 9 20...
Page 514: ...IA 32 Intel Architecture Optimization B 60...
Page 536: ...IA 32 Intel Architecture Optimization C 22...