Intel ARCHITECTURE IA-32, Reference Manual, Page: 512 / 568

IA-32 Intel® Architecture Optimization
B-58
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Some events, such as writebacks, may have non-deterministic
behavior for different runs. In such a case, only measurements
collected in the same run yield meaningful ratio values.
Notes on Selected Events
This section provides event-specific notes for interpreting performance
events listed in Table A-9 of the
IA-32 Intel® Architecture Software
Developer’s Manual, Volume 3B .
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L2_Reject_Cycles, event number 30H
This event counts the cycles during which the L2 cache rejected new
access requests.
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L2_No_Request_Cycles, event number 32H
This event counts cycles during which no requests from the L1 or
prefetches to the L2 cache were issued.
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Unhalted_Core_Cycles, event number 3C, unit mask 00H
This event counts the smallest unit of time recognized by an active
core.
In many operating systems (OS), the idle task is implemented using
HLT instruction. In such operating systems, clockticks for the idle
task are not counted. A transition due to Enhanced Intel SpeedStep
Technology may change the operating frequency of a core.
Therefore, using this event to initiate time-based sampling can
create artifacts.
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Unhalted_Ref_Cycles, event number 3C, unit mask 01H
This event guarantees a uniform interval for each cycle being
counted. Specifically, counts increment at bus clock cycles while the
core is active. The cycles can be converted to core clock domain by
multiplying the bus ratio which sets the core clock frequency.