3.1.7.2.1. PFL II Parameters
Table 23.
PFL II General Parameters
Options
Value
Description
What operating mode
will be used?
• Flash Programming
• FPGA Configuration
• Flash Programming and FPGA Configuration
Specifies the operating mode of flash programming and FPGA configuration control in one
IP core or separate these functions into individual blocks and functionality.
What is the targeted
flash?
• CFI Parallel Flash
• Quad SPI Flash
Specifies the flash memory device connected to the PFL II IP core.
Set flash bus pins to
tri-state when not in
use
• On
• Off
Allows the PFL II IP core to tri-state all pins interfacing with the flash memory device
when the PFL II IP core does not require access to the flash memory.
Table 24.
PFL II Flash Interface Setting Parameters
Options
Value
Description
How many flash
devices will be used?
• 1–16
Specifies the number of flash memory devices connected to the PFL II IP core.
What's the largest
flash device that will
be used?
• 8 Mbit–4 Gbit
Specifies the density of the flash memory device to be programmed or used for FPGA
configuration. If you have more than one flash memory device connected to the PFL II IP
core, specify the largest flash memory device density.
For dual CFI flash, select the density that is equivalent to the sum of the density of two
flash memories. For example, if you use two 512-Mb CFI flashes, you must select CFI 1
Gbit.
What is the flash
interface data width
• 8
• 16
• 32
Specifies the flash data width in bits. The flash data width depends on the flash memory
device you use. For multiple flash memory device support, the data width must be the
same for all connected flash memory devices.
Select the flash data width that is equivalent to the sum of the data width of two flash
memories. For example, if you are targeting dual solution, you must select 32 bits
because each CFI flash data width is 16 bits.
Allow user to control
FLASH_NRESET pin
• On
• Off
Creates a
FLASH_NRESET
pin in the PFL II IP core to connect to the reset pin of the flash
memory device. A low signal resets the flash memory device. In burst mode, this pin is
available by default.
When using a Cypress GL flash memory, connect this pin to the
RESET
pin of the flash
memory.
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
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