Note:
Coming out of reset, you cannot rely on the value of registers with initial conditions unless you gate your system reset using
one of the following options:
•
Designs that include the Reset Release IP must route
nINIT_DONE
to the system reset.
•
Designs that do not include the Reset Release IP must route INIT_DONE to an external pin and feed
INIT_DONE
back into
the FPGA as an input to system reset.
4.5.3. Embedded Memory Block Initial Conditions
Initialized content of embedded memory blocks is stable during configuration. However, designs that contain logic to modify
embedded memory can result in spurious writes. Spurious writes can occur if you fail to gate the write enable with an
appropriate reset.
4.5.4. Protecting State Machine Logic
To guarantee correct operation of state machines, your reset logic must hold the FPGA fabric in reset until the entire fabric
enters user mode.
The following example shows how an inadequate reset strategy might result in an illegal state in a one-hot state machine. In
this example, the design does not reset any of the state machine registers. The state machine design depends on registers
entering an initial state. Without an adequate reset, this state machine begins operating when part of the device is active.
Nearby logic included in the state machine remains frozen, before
INIT_DONE
asserts.
Figure 59.
Partially Initialized Design - INIT_DONE = 0
O
O
Register A
Register B
Register C
Functional (Row N)
In Reset (Row N+1)
1
4. Including the Reset Release Intel FPGA IP in Your Design
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