Intel Agilex Series Configuration User Manual Download

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Configuration Clock Source

AS_CLK

Frequency (MHz)

71.5

100
125
166

Note:

The configuration fails if the firmware receives bitstream with an invalid

AS_CLK

setting. For firmware in Intel Quartus Prime

software version before 21.1, if

AS_CLK

is set incorrectly, the firmware defaults the

AS_CLK

frequency to 50 MHz to complete

the AS x4 configuration.

3.2.9. Active Serial Configuration Software Settings

You must set the parameters in the Device and Pin Options of the Intel Quartus Prime software when using the AS

configuration scheme.

To set the parameters for AS configuration scheme, complete the following steps:
1. On the Assignments menu, click Device.
2. In the Device and Pin Options select the Configuration category.

a. Select Active Serial x4 from the Configuration scheme drop down menu.

3. Intel Agilex Configuration Schemes

683673 | 2021.10.29

Intel

Agilex

™

Configuration User Guide

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116

Summary of Contents for Agilex Series

Page 1: ...Intel Agilex Configuration User Guide Updated for Intel Quartus Prime Design Suite 21 3 Online Version Send Feedback UG 20205 ID 683673 Version 2021 10 29...

Page 2: ...Device Configuration Pins for Optional Configuration Signals 31 2 6 Configuration Clocks 48 2 6 1 Setting Configuration Clock Source 48 2 6 2 OSC_CLK_1 Clock Input 49 2 7 Intel Agilex Configuration Ti...

Page 3: ...AG Configuration Scheme 132 4 Including the Reset Release Intel FPGA IP in Your Design 134 4 1 Understanding the Reset Release IP Requirement 135 4 2 Instantiating the Reset Release IP In Your Design...

Page 4: ...for Factory Image and One Application Image 196 5 6 3 Programming Flash Memory with the Initial Remote System Update Image 200 5 6 4 Reconfiguring the Device with an Application or Factory Image 201...

Page 5: ...8 Intel Agilex Configuration User Guide Archives 217 9 Document Revision History for the Intel Agilex Configuration User Guide 218 Contents Send Feedback Intel Agilex Configuration User Guide 5...

Page 6: ...the master and controls configuration The FPGA acts as the slave device All Intel Agilex configuration schemes support design security and partial reconfiguration All Intel Agilex active configuratio...

Page 7: ...he AVST_READY and AVST_VALID pins Because the time to decompress the incoming bitstream varies backpressure support is necessary to transfer data to the Intel Agilex device For more information about...

Page 8: ...2 The host device uses the CvP PCIe link to configure your design in the core fabric CvP update mode updates the FPGA core image using the PCIe link already established from a previous full chip confi...

Page 9: ...uses the SDM to report that the memory is missing Consequently configuration fails Related Information Avalon Interface Specifications Intel Agilex Configuration via Protocol CvP Implementation User G...

Page 10: ...er Guide and Intel Agilex Power Management User Guide for more information about those features Related Information SDM Pin Mapping on page 28 Intel Agilex Power Management User Guide Intel Agilex Con...

Page 11: ...pin female plug Intel FPGA Ethernet Cable formerly the Ethernet Blaster II JTAG AS 10 pin female plug The Intel FPGAs and Programmable Devices Download Cables provides more information about the downl...

Page 12: ...to distribute the configuration bitstream to Local Sector Managers LSMs You cannot access this network LSMs The LSM is a microprocessor Each configuration sector includes an LSM The LSM parses configu...

Page 13: ...uration Sector Configuration Network Local Sector Manager LSM Local Sector Manager LSM Local Sector Manager LSM Local Sector Manager LSM Intel Agilex Blocks All Family Variants Related Information Int...

Page 14: ...onfiguration bitstream is from a trusted source All Intel Agilex support authentication Encryption Encryption protects the configuration bitstream or confidential data from unauthorized third party ac...

Page 15: ...n Chip ID Serial Flash Mailbox Client IP Partial Reconfiguration PR IP OCRAM Hard IP in SDM External Hard IP Soft IP Legend External PR Controller IP Temperature Sensor IP Voltage Sensor IP Here is an...

Page 16: ...the SDM firmware that matches the Intel Quartus Prime Pro Edition Release to the bitstream generated from the sof Depending on the configuration scheme you specify the resulting file can be in any of...

Page 17: ...oning just before the HPS exits reset Note that FPGA First option does not allow FPGA reconfiguration by using HPS This user guide defines a state when the FPGA is functional Configuration and initial...

Page 18: ...O pin at any point during the power up and power down should not exceed the I O buffer power supply rail of the bank When using pin in the GPIO bank with 1 5V VCCIO_PIO the pin voltage must not exceed...

Page 19: ...nSTATUS reflects the current configuration state nCONFIG must only change when it has the same value as nSTATUS Note To receive a valid nSTATUS response from the device your host must only monitor thi...

Page 20: ...s and enters user mode The entire device does not enter user mode simultaneously Intel requires you to include reset release as described in the Including the Reset Release Intel FPGA IP in Your Desig...

Page 21: ...complete successfully nCONFIG should continue to be driven high until after nSTATUS has returned back to high state If an error occurs during JTAG configuration the SDM does not change the state of th...

Page 22: ...or nSTATUS and enable device power cycling if needed Note that in the case of a double bit ECC error in the SDM RAM nSTATUS is also asserted low and stays low Related Information Standard non RSU Imag...

Page 23: ...ric For nSTATUS low pulse duration refer to the t STO parameter in the Intel Device Datasheet nCONFIG HIGH nSTATUS HIGH Configuration Error nSTATUS LOW Pulse nCONFIG LOW Initialization complete nCONFI...

Page 24: ...l of the bank When using pin in the GPIO bank with 1 5V VCCIO_PIO the pin voltage must not exceed the VCCIO_PIO rail or 1 2V whichever is lower SDM Startup The SDM samples the MSEL pins during power o...

Page 25: ...igh impedance state The device enters user mode After CONF_DONE asserts and before INIT_DONE asserts parts of the device start to enter user mode The assertion of INIT_DONE indicates that the entire d...

Page 26: ...pe the FPGA Sample MSEL pins Read fuses Run the SDM boot ROM code Reset the SDM Reset the HPS Note When using QSPI you can use Remote System Update RSU to load a specific image with the same device re...

Page 27: ...l testing Designs that include many transceivers require an auxiliary power supply to operate reliably Intel Quartus Prime Pro Edition software allows you to configure the HPS prior to FPGA configurat...

Page 28: ...emain weakly pulled up 3 In approximately 10 ms the SDM I O pins take on the state that your design specifies 4 After device cleaning the SDM reads pin information from firmware and restores the pin s...

Page 29: ...IO10 AVSTx8_DATA7 SDM_IO11 AVSTx8_VALID SDM_IO12 SDM_IO13 AVSTx8_DATA5 SDM_IO14 AVSTx8_CLK SDM_IO15 AVSTx8_DATA6 AS_nRST SDM_IO16 2 5 2 MSEL Settings After power on MSEL 2 0 pins specify the configura...

Page 30: ...s dialog box in the Intel Quartus Prime Software 5 If you use AS Fast mode you must ramp all power supplies to the recommended operating condition within 10 ms This ramp up requirement ensures that th...

Page 31: ...essful The SDM drives the CONF_DONE signal high after successfully receiving full bitstream The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode These signals are impo...

Page 32: ...IO15 SDM_IO16 SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 INIT_DONE SDM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10...

Page 33: ...13 SDM_IO14 SDM_IO15 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12...

Page 34: ...SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 nCATTRIP SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_I...

Page 35: ...about PWRMGT_SCL PWRMGT_SDA and PWRMGT_ALERT signals 2 5 3 1 Specifying Optional Configuration Pins You enable and assign the SDM I O pins using the Intel Quartus Prime software Complete the following...

Page 36: ...5 3 1 1 nCONFIG The nCONFIG pin is a dedicated input pin of the SDM nCONFIG has two functions Hold off initial configuration Initiate FPGA reconfiguration 2 Intel Agilex Configuration Details 683673...

Page 37: ...pt after an error For example after POR nSTATUS asserts after nCONFIG asserts When the host drives nCONFIG high the Intel Agilex device drives nSTATUS high In previous device families the deassertion...

Page 38: ...o and during configuration CONF_DONE asserts when the device finishes receiving configuration data INIT_DONE asserts when the device enters user mode Note The entire device does not enter user mode si...

Page 39: ...Figure 10 Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software 2 Intel Agilex Configuration Details 683673 2021 10 29 Send Feedback Intel Agilex Configuration User Guide 39...

Page 40: ...e pins Once the device enters user mode these pins can function either as GPIOs or as tri state inputs If you use these pins as GPIOs make the following assignments Set VCCIO of the I O bank at 1 2 V...

Page 41: ...restrictions You cannot use the Avalon ST interface for partial reconfiguration PR You cannot use the Avalon ST pins in user mode in designs that include the HPS This restriction means that you cannot...

Page 42: ...1 8 V LVCMOS 8 mA Disable Fast AS_nRST SDM_IO15 Output 1 8 V LVCMOS 8 mA Disable Fast Table 8 Intel Agilex AS 4 Configuration Scheme Unused Configuration Pins For the unused configuration pins the dr...

Page 43: ...S Schmitt Trigger Disable AVSTx8_CLK SDM_IO14 Input 1 8 V LVCMOS Schmitt Trigger Disable AVSTx8_DATA6 SDM_IO15 Input 1 8 V LVCMOS Schmitt Trigger Disable Table 10 Intel Agilex Avalon Streaming Interfa...

Page 44: ...ion I O Standard Schmitt Trigger TTL Input Weak Pull Up Pull Down Drive Strength Open Drain Slew Rate PWRMGT_SCL Bidirectional 1 8V LVCMOS Schmitt Trigger Weak pull up with 20 k resistor 2 mA Enable S...

Page 45: ...on IBIS Models for Intel Devices 2 5 3 4 SDM I O Pins for Power Management and SmartVID SDM pins are also available for the SmartVID power management feature for V and E devices Intel recommends that...

Page 46: ...he Page payload available range is between 0x00 and 0xFF Note Prior the Intel Quartus Prime Pro Edition software release the Page command selected all banks by default Figure 13 Specifying the Page Co...

Page 47: ...Related Information Intel Agilex Power Management User Guide 2 Intel Agilex Configuration Details 683673 2021 10 29 Send Feedback Intel Agilex Configuration User Guide 47...

Page 48: ...ify the configuration clock source by selecting either the internal oscillator or OSC_CLK_1 with the supported frequency By default the SDM uses the internal oscillator for device configuration Specif...

Page 49: ...SDM can use either clock source for the remainder of device configuration If you use the internal oscillator you can leave the OSC_CLK_1 unconnected If you use transceivers you must provide an extern...

Page 50: ...rements for Configuration After Powering Cycling the Device After a power down when you specify OSC_CLK_1 for configuration the Intel Agilex device uses the internal oscillator to load the first secti...

Page 51: ...Modes in P tile designs The data in this table is preliminary Device Bitstream File Size MB Configuration Time Estimation ms AS x4 8 AVST x8 AVST x16 AVST x32 AGF 012 AGF 014 2 5 250 160 150 N A 26 5...

Page 52: ...Figure 14 Compressed sof Selection in the Intel Quartus Prime Pro Edition 2 Intel Agilex Configuration Details 683673 2021 10 29 Intel Agilex Configuration User Guide Send Feedback 52...

Page 53: ...on Scheme You can use an 8 16 or 32 bit Avalon ST configuration data bus You specify SDM I O pin functions using the Device Device and Pin Options Configuration dialog box in the Intel Quartus Prime s...

Page 54: ...power requirements Attention Access to the I O pins located in bank 3A with pin index 91 95 is not allowed for the AVSTx16 or x32 configuration scheme You must leave these pins unconnected For more i...

Page 55: ...guration scheme A CPLD with PFL II IP and common flash interface CFI flash or Quad SPI flash memory A custom host typically a microprocessor with any external memory The Intel FPGA Download Cable II t...

Page 56: ...pe Use the PFL II IP core via a JTAG header to write the pof to an external CFI flash or serial flash device Raw Binary File rbf You can also use the rbf with the Avalon ST configuration scheme and an...

Page 57: ...Device and Pin Options dialog box select the Configuration category 3 In the Configuration window in the Configuration scheme dropdown list select the appropriate Avalon ST bus width 4 Click OK to con...

Page 58: ...d may assert AVST_VALID signal any time after the assertion of AVST_READY signal The host must monitor the AVST_READY signal throughout the configuration Note To receive a valid nSTATUS response from...

Page 59: ...ady_reg2 signal is the AVST_READY signal that is synchronous to AVST_CLK Note You must properly constrain the AVST_CLK and AVST_DATA signals at the host Perform timing analysis on both signals between...

Page 60: ...riting 32 bit Data For a x32 data bus the first byte in the file is the least significant byte of the configuration double word and the fourth byte is the most significant byte Double Word 01EE1B02 LS...

Page 61: ...iguration Control Signals Non Volatile Memory Interface External Non Volatile Memory Access Port rbf or pof CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_ncon...

Page 62: ...Non Volatile Memory Interface External Non Volatile Memory Access Port rbf or pof CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_nconfig fpga_data 15 0 10k MSE...

Page 63: ...Non Volatile Memory Interface External Non Volatile Memory Access Port rbf or pof CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_nconfig fpga_data 31 0 10k MSE...

Page 64: ...ata is not transferred when AVST_READY and AVST_VALID are low The AVST_CLK and AVSTx8_CLK clock signals must run continuously until CONF_DONE asserts Debugging Suggestions Review the general Configura...

Page 65: ...e using JTAG interface Configure the Intel Agilex device with the Avalon ST configuration scheme from the flash memory device Note Intel Agilex device configuration is not available in the current rel...

Page 66: ...terface External Host CFI Flash Memory Configuration Data Common Flash Interface PFL II Quartus Prime Software using JTAG The PFL II IP core supports dual flash memory devices in burst read mode to ac...

Page 67: ...16 16 ADDR 24 0 NCE NWE NOE DATA 15 0 ADDR 24 0 NCE NWE NOE DATA 15 0 flash_addr 24 0 flash_nce flash_nwe flash_noe flash_data 31 0 fpga_conf_done fpga_nstatus fpga_nconfig avst_data avst_clk CONF_DO...

Page 68: ...address of the page The Intel Quartus Prime software aligns the pages on a 128 KB boundary If the first valid start address is 0x000000 the next valid start address is an multiple of 0x20000 3 1 7 1 3...

Page 69: ...nd FPGA Configuration for the What operating mode will be used parameter on the General tab The following figure shows the FPGA Configuration option Figure 22 General Tab of the PFL II IP Select FPGA...

Page 70: ...is Start address must match the address you specify for What is the byte address of the option bits in hex when specifying the PFL II IP parameters The Intel Quartus Prime Programming File Generator g...

Page 71: ...ess 0x2C 0x2F Page 5 end address 0x30 0x33 Page 6 start address 0x34 0x37 Page 6 end address 0x38 0x3B Page 7 start address 0x3C 0x3F Page 7 end address 0x40 0x7F Reserved 0x80 10 pof version 0x81 0xF...

Page 72: ...the start address Table 20 Start Address Bit Content Bit Width Description 31 11 21 Addressable start address 10 1 10 Reserved bits 0 1 Page valid bit 0 Valid 1 Error Table 21 End Address Bit Content...

Page 73: ...32 b00000000110101001011100011000011 0xD4B8C3 The start and end address must be correlated with the start and end address for each page printed in the map file 3 1 7 1 5 Implementing Page Mode and Op...

Page 74: ...ress Page Valid Page 0 Address Page Valid End Address 0x000000 8 Bits 32 Bits The following figure shows the layout of the option bits for a single page Because the start address must be on an 8 KB bo...

Page 75: ...001 Page Start Address 17 13 Page Start Address 25 18 Page Start Address 33 26 Page End Address 9 2 Page End Address 17 10 Page End Address 25 18 0x002004 0x002005 0x002006 Page End Address 33 26 Page...

Page 76: ...vice configuration design targeting a MAX10 MAX V MAX II device involves three steps 1 Generate the AVST design for the MAX device with the default option address 2 Create the Intel Agilex pof file in...

Page 77: ...Prime Programmer Program the MAX II and Flash Devices MAX II configures the FPGA with the configuration data from the Flash Device Compileand obtainthe FPGA sof s Convertto pofforthe Targeted Flash C...

Page 78: ...FPGA configuration If you have more than one flash memory device connected to the PFL II IP core specify the largest flash memory device density For dual CFI flash select the density that is equivalen...

Page 79: ...FPGA can use for configuration The PFL II IP core can divide the frequency of the input clock maximum by two What is the flash access time Provide the access time from the flash data sheet Specifies t...

Page 80: ...the period before the watchdog timer times out The watchdog timer runs at the pfl_clk frequency Time period before the watchdog timer times out Specifies the time out period for the watchdog timer Th...

Page 81: ...e if you are only using the PFL II IP for flash programming fpga_conf_done Input 10 k Pull Up Resistor Connects to the CONF_DONE pin of the FPGA The FPGA releases the pin high if the configuration is...

Page 82: ...ash memory devices in the chain flash_nwe Output Connects to the nWE pin of the flash memory device When low enables write operations to the flash memory device flash_noe Output Connects to the nOE pi...

Page 83: ...signal high or low for at least two pfl_clk clock cycles pfl_watchdog_error Output When high indicates an error condition to the watchdog timer Related Information Avalon Interface Specifications 3 1...

Page 84: ...sh memory device for the following purposes To write the initialization data To store your design source code to implement the read and initialization control with the host logic 3 1 7 3 2 Mapping PFL...

Page 85: ...bits 23 22 21 3 2 1 address 23 bits PFL II Flash Memory Figure 30 Cypress and Micron M28 M29 Flash Memory in 8 Bit Mode The flash memory addresses in Cypress 8 bit flash shifts one bit up Address bit...

Page 86: ...h Programming and FPGA Configuration 3 In the same tab for What is the targeted flash select CFI Parallel Flash 4 Specify the parameters on the Flash Interface Settings tab a Select 1 for a single fla...

Page 87: ...es the configuration controller Note By default all unused pins are set to ground When programming the configuration flash memory device through the host JTAG pins you must tri state the FPGA configur...

Page 88: ...nchronize the AVST_READY signal to the AVST_CLK signal using a 2 stage register synchronizer set_false_path from get_ports avst_ready to 3 1 7 4 2 PFL II IP Recommended Design Constraints for Using QS...

Page 89: ...o4 flash_dc1_io5 set_input_delay clock FLASH_CLK min in_min_dly get_ports flash_dc1_io1 flash_dc1_io3 flash_dc1_io4 flash_dc1_io5 3 1 7 4 3 PFL II IP Recommended Design Constraints for using CFI Flash...

Page 90: ...0 set flash_tco_max 7 000 set flash_tco_min 0 000 set normal_in_max_dly expr flash_data_tracemax flash_tco_max flash_noe_tracemax set normal_in_min_dly expr flash_data_tracemin flash_tco_min flash_noe...

Page 91: ...atic signals such as reset and configuration signals fpga_conf_done fpga_nstatus that are stable for a long periods of time set_false_path from get_ports fpga_pgm to Example 13 Set input delay to pfl_...

Page 92: ...y to flash_nreset output pin The flash_nreset output pin is available in Burst mode only set_output_delay add_delay max clock get_clocks FLASH_CLK flash_out_max_dly get_ports flash_nreset set_output_d...

Page 93: ...Generator 2 For Device family select Intel Agilex 3 For Configuration mode select Avalon ST configuration scheme that you plan to use 4 For Output directory click Browse to select your output file dir...

Page 94: ...ut Files To Generate Input File Source and Configuration Device Generate Selected Files 8 To specify a sof that contains the configuration bitstream on the Input Files tab click Add Bitstream 3 Intel...

Page 95: ...lel flash devices 11 Click OPTIONS and then Edit In the Edit Partition dialog box specify the Start address of the Options in flash memory This address must match the address you specify for What is t...

Page 96: ...for Flash Device Start address 12 With the flash device selected click Add Partition to specify a partition in flash memory 3 Intel Agilex Configuration Schemes 683673 2021 10 29 Intel Agilex Configur...

Page 97: ...to use The following modes are available Auto For the tool to automatically allocates a block in the flash device to store the data Block To specify the start and end address of the flash partition S...

Page 98: ...e For Block and Start options specify the address information 3 Intel Agilex Configuration Schemes 683673 2021 10 29 Intel Agilex Configuration User Guide Send Feedback 98...

Page 99: ...art to program the CPLD and ash memory device 3 1 7 5 3 Programming CPLDs and Flash Memory Devices Separately Follow these instructions to program the CPLD and the ash memory devices separately 1 Open...

Page 100: ...tible CFI flash memory device in the PFL II supported flash database using the Define New CFI Flash Device function To add a new CFI flash memory device to the database or update a CFI flash memory in...

Page 101: ...lash extended device identifier only applicable for AMD compatible CFI flash memory device Flash device is Intel compatible Turn on the option if the CFI flash is Intel compatible Typical word program...

Page 102: ...ncluding I O configuration and FPGA core configuration Designs including an HPS can use the HPS to access serial flash memory after the initial configuration Note The serial flash configuration device...

Page 103: ...on in the SDM Start state After the SDM samples the MSEL pins the MSEL pins become active low chips selects For AS x4 designs using one flash device AS_nCSOO asserts low when the SDM starts to communi...

Page 104: ...ignal deasserts The following block diagram illustrates the components and design flow using the AS configuration scheme Figure 37 Components and Design Flow for jic Programming Quartus Software flow...

Page 105: ...the Intel Agilex device The SDM can then load the flash device with the Intel Agilex design Raw Programming Data File rpd Stores data for configuration with a third party programming hardware You gen...

Page 106: ...0 pin male header DATA 3 0 DCLK nCS Configuration Control Signals Optional Monitoring 10k Optional Configuration Data Signals To JTAG Header or JTAG Chain MSEL VCCIO_SDM 3 4 TCK TDO TDI TMS JTAG Confi...

Page 107: ...th Multiple Serial Flash Devices Pin 1 RUP RDN RUP TCK TDO TMS OPEN TDI GND VCCIO_SDM OPEN OPEN GND GND VCCIO_SDM Intel FPGA nCONFIG nSTATUS CONF_DONE INIT_DONE OSC_CLK_1 MSEL 2 0 AS_DATA 3 0 Config A...

Page 108: ...nd Clock Source This table is preliminary Capacitance Loading pF Maximum Supported AS_CLK MHz OSC_CLK_1 MHz Internal Oscillator MHz 10 166 125 115 30 100 77 37 71 5 77 80 50 58 140 25 25 Related Infor...

Page 109: ...20 77 MHz 0 20 58 MHz 0 20 25 MHz 0 24 OSC_CLK_1 166 MHz 0 13 5 125 Mhz 0 18 100 MHz 0 24 71 5 MHz 0 35 50 MHz 0 24 25 MHz 0 24 Note For more information about the timing parameters refer to the Inte...

Page 110: ...system using the Intel FPGA Download Cable II or Intel FPGA Ethernet Cable You have the following two in system programming options Active Serial JTAG 3 2 6 1 Programming Serial Flash Devices using t...

Page 111: ...Third Party Programmer AS_DATA 0 AS x4 Flash Intel FPGA 10 k nSTATUS nCONFIG CONF_DONE OSC_CLK_1 DATA0 DATA1 DATA2 DATA3 DCLK nCS AS_DATA 1 AS_DATA 2 AS_DATA 3 AS_CLK 4 7 k VCCIO_SDM GND VCCIO_SDM VC...

Page 112: ...evice through JTAG interface and programs the serial flash device Figure 43 Programming Your Serial Configuration Device Using JTAG Intel FPGA Board Secure Device Manager AS x4 Flash JTAG Interface JT...

Page 113: ...S_DATA 2 AS_DATA 3 AS_CLK 4 7 k GND GND VCCIO_SDM VCCIO_SDM 10 k VCCIO_SDM 10 k 4 7 k VCCIO_SDM MSEL 0 AS_nCSO 0 MSEL 1 MSEL 2 ASfastmode PullMSEL 1 lowusing4 7 k resistor ASnormalmode PullMSEL 1 high...

Page 114: ...mmer interfaces to the SDM device through JTAG interface and programs the serial flash device 3 2 7 Serial Flash Memory Layout Serial flash devices store the configuration data in sections The followi...

Page 115: ...2 Mb 1 Gb and 2 Gb Micron and Macronix both offer Quad SPI memories with a density range of 128Mb 2Gb 3 2 8 AS_CLK The Intel Agilex device drives AS_CLK to the serial flash device An internal oscillat...

Page 116: ...2 9 Active Serial Configuration Software Settings You must set the parameters in the Device and Pin Options of the Intel Quartus Prime software when using the AS configuration scheme To set the parame...

Page 117: ...ation You can use the Programming File Generator to generate programming files for alternative device programming methods such as the jic for flash programming or rpd for third party programmer config...

Page 118: ...G Indirect Configuration File jic and Raw Programming Data File rpd file types Figure 46 Programming File Generator Output Files Device Family Configuration Mode Output Directory Name Output Files Req...

Page 119: ...list or define a custom device using the available menu options For more information about defining a custom configuration device refer to the Configuration Device Tab Settings Programming File Genera...

Page 120: ...Figure 48 Programming File Generator Configuration Device Tab 3 Intel Agilex Configuration Schemes 683673 2021 10 29 Intel Agilex Configuration User Guide Send Feedback 120...

Page 121: ...this file to regenerate the programming file by running the following command quartus_pfg c configuration_file pfg Related Information Intel Quartus Prime Pro Edition User Guide Programmer For compre...

Page 122: ...Programmer window click Hardware Setup and select the desired download cable 2 In the Mode list select JTAG 3 Select the device to be programmed and click Add File 4 Select the jic to be programmed t...

Page 123: ...irement ensures that the AS x4 device is within its operating voltage range when the Intel Agilex device begins accessing the AS x4 device When using AS fast mode all power supplies to the Intel Agile...

Page 124: ...ice You should generate the rpd as big endian If you are using the OSC_CLK_1 clock source for configuration ensure OSC_CLK_1 is free running and stable before SDM starts to load a bitstream from the Q...

Page 125: ...gabits per second Mode Data Width bits Max Clock Rate Max Data Rate MSEL 2 0 Passive JTAG 1 30 MHz 30 Mbps 3 b111 Note The JTAG port has the highest priority and overrides the MSEL pin settings Conseq...

Page 126: ...ming This is the simplest device configuration scheme You do not have to use the File Programming File Generator to convert the sof file to a pof Figure 49 JTAG Configuration Scheme Quartus Prime Comp...

Page 127: ...To configure a single device in a JTAG chain the programming software sets the other devices to bypass mode A device in bypass mode transfers the programming data from the TDI pin to the TDO pin thro...

Page 128: ...Control Signals JTAG Configuration Pins Optional Monitoring To JTAG Header or JTAG Chain 10k MSEL VCCIO_SDM 3 Pin 1 Download cable 10 pin male header JTAG mode RUP RDN RUP TCK TDO TMS OPEN TDI GND VCC...

Page 129: ...3 3 2 2 JTAG Single Device Configuration using a Microprocessor Refer to the Intel Agilex Device Family Pin Connection Guidelines for additional information about individual pin usage and requirement...

Page 130: ...al Monitoring 10k Optional MSEL VCCIO_SDM 3 JAM Player 10k VCCIO_SDM Resistorvaluescanvarybetween1k to10k Performsignalintegrityanalysistoselect theresistorvalueforyoursetup VCCIO_SDM RDN GND RUP 3 3...

Page 131: ...ATUS nCONFIG MSEL 2 0 CONF_DONE TMS TCK TDI TDO nSTATUS nCONFIG MSEL 2 0 CONF_DONE Intel FPGA Intel FPGA Intel FPGA TMS TCK TDI TDO nSTATUS nCONFIG MSEL 2 0 CONF_DONE Download cable 10 pin male header...

Page 132: ...ugging tips for JTAG Verify that the JTAG pin connections are correct If JTAG configuration is failing check that the FPGA has successfully powered up and exited POR One strategy is to check the hand...

Page 133: ...version In earlier Intel Quartus Prime software versions the RSU_STATUS is not cleared after the JTAG reconfiguration Starting with the Intel Quartus Prime 20 3 version the system clears the RSU_STAT...

Page 134: ...Reset Application Logic Intel FPGA Reset Release IP View the video guide below for a quick walk through to understand the importance of using Reset Release Intel FPGA IP and how to include it in your...

Page 135: ...xactly the same time as has always been the case in previous families The continual increases in clock frequency device size and design complexity now necessitate a reset strategy that considers the p...

Page 136: ...write enable of design blocks such as embedded memory blocks state machine and shift registers To synchronously drive register reset input ports in your design Attention If you use multiple Reset Rele...

Page 137: ...IP directory and specify a file name for the Reset Release IP Then click Create The Reset Release IP is now included in your project 4 3 Gating the PLL Reset Signal In older FPGA device families desi...

Page 138: ...ull FPGA core configuration and subsequent full FPGA core reconfigurations The Reset Release IP is not necessary to prevent interaction between the static and PR personas during the PR process For mor...

Page 139: ...uld begin to operate while other logic is still frozen The INIT_DONE signal asserts when all the LSMs have entered user mode Figure 57 Releasing LAB Rows and Registers in the LABs Sequentially and Asy...

Page 140: ...4 The SDM uses the configuration logic to enable and initialize user registers in the LABs DSP and embedded memory blocks 5 The SDM drives INIT_DONE to indicate that the device has fully entered user...

Page 141: ...Figure 58 Disabling Register Initialization During Power On Turn On 4 Including the Reset Release Intel FPGA IP in Your Design 683673 2021 10 29 Send Feedback Intel Agilex Configuration User Guide 141...

Page 142: ...te reset 4 5 4 Protecting State Machine Logic To guarantee correct operation of state machines your reset logic must hold the FPGA fabric in reset until the entire fabric enters user mode The followin...

Page 143: ...1 1 O Register A Register B Register C Error 1 Functional Row N Functional Row N 1 The entire fabric is now in user mode The state machine enters an illegal or unknown state with two ones in a one hot...

Page 144: ...FPGA drives the RSU For the Intel Agilex SoC devices HPS can drive the RSU process For passive configuration schemes an external host implements remote system update rather than the Intel Agilex devic...

Page 145: ...emote Connection Remote Connection Data Data Intel FPGA Note An Intel Agilex version of the Intel Stratix 10 SoC Remote System Update RSU User Guide is not yet available The RSU SoC implementation in...

Page 146: ...ry Image pin assignment PLL settings for the external clock source This optional clock source drives OSC_CLK_1 For more information refer to OSC_CLK_1 Clock Input Quad SPI pins Configuration pointer b...

Page 147: ...oes an application image Initial RSU flash image Contains the factory image the application images the decision firmware and the associated RSU data structures Factory update image An image that updat...

Page 148: ...ire a Mailbox Client Intel FPGA IP as shown in the figure below The Mailbox Client sends and receives remote system update operation commands and responses such as QSPI_READ and QSPI_WRITE Figure 62 I...

Page 149: ...n image contains logic to implement the custom application The application image must also contain logic to obtain new application images and store the images in the flash memory Depending on the stor...

Page 150: ...Pin is asserted No Yes nCONFIG Asserted Decision Firmware Decision Firmware Decision Firmware Decision Firmware Sub Partition Table Configuration Pointer Block Remote Update to Factory Image Remote U...

Page 151: ...ies the next application image from the list If none of the application images load successfully the SDM loads the factory image 6 If loading the factory image fails you can recover by reprogramming t...

Page 152: ...rity 1 Application Image3 highest priority 2 Application Image2 3 Application image1 4 Application image0 lowest priority Application Image3 Application Image2 and Application Image1 are corrupted RSU...

Page 153: ...t Address Offset M 64 KB Application Image2 Corrupt Address Offset O 64 KB Current Image Last Failing Image Highest Priority Failing Image Application Image3 Corrupt Address Offset P 64 KB Related Inf...

Page 154: ...y partition slot starting from a new sector boundary in the flash device 3 Trigger reconfiguration to load the update image from the starting address using one of the following methods Trigger reconfi...

Page 155: ...Avalon Master Bridge IP as a remote system update host controller The remote system update host controller controls the remote system update function by sending commands to and receiving responses fro...

Page 156: ...an application image or vice versa ii From an application image to another application image b Erasing the application image c Adding an application image d Updating an application or factory image Re...

Page 157: ...ote The LENGTH field in the command header must match the command length of corresponding command Your client must read all the response words even if your client does not interpret all the response w...

Page 158: ...onnect the quad SPI reset pin to any external host RSU SDM Command Use Case Important All RSU related SDM commands RSU_IMAGE_UPDATE RSU_GET_SPT RSU_STATUS and RSU_NOTIFY are only valid when the FPGA l...

Page 159: ...t the RSU uses SPT0 and SPT1 The 4 word response contains the following information Word Name Description 0 SPT0 63 32 SPT0 address in quad SPI flash 1 SPT0 31 0 2 SPT1 63 32 SPT1 address in quad SPI...

Page 160: ...l Quartus Prime software version 21 3 1 the following values represent the major and minor Quartus release numbers and the Quartus update number Bit 23 16 8 d21 8 h15 Bit 15 8 8 d3 8 h3 Bit 7 0 8 d1 8...

Page 161: ...ng images the remainder of the remaining words of the status information do not store valid information Note A rising edge on nCONFIG to reconfigure from ASx4 does not clear this field Information abo...

Page 162: ...counter back to zero as if the current image was successfully loaded for the first time 0x00060000 Clear error status information All other values are reserved This command is not available before ver...

Page 163: ...AS x4 configuration For the Avalon streaming interface Avalon ST configuration scheme you must connect QSPI flash memories to GPIO pins Important When resetting quad SPI you must follow instructions s...

Page 164: ...tiples of 0x400 to erase 4 KB 100 words of data This option is the minimum erase size 0x2000 to erase 32 KB 500 words of data 0x4000 to erase 64 KB 1000 words of data A successful erase returns the OK...

Page 165: ...tting quad SPI you must follow instructions specified in Resetting Quad SPI Flash on page 158 QSPI_SEND_ DEVICE_OP 37 1 0 Sends a command opcode to the quad SPI Takes one argument The opcode to send t...

Page 166: ...rror indicates one of the following conditions An unaligned address An address range problem A read permission problem An invalid chip select value displaying value of more than 3 An invalid address i...

Page 167: ...due to an internal error HPS HPS is busy when in HPS reconfiguration process or HPS cold reset 2FF ALT_SDM_MBOX_RESP_NO_ VALID_RESP_AVAILABLE Indicates that there is no valid response available 3FF A...

Page 168: ...Continue with the next operation 82 EFUSE_SYSTEM_FAILURE Attempt reconfiguration or power cycle If error persists after reconfiguration or power cycle the device may be damaged and unrecoverable 100 N...

Page 169: ...to Factory Direct to Factory 5 4 1 2 RSU Image Layout in Flash SDM Perspective In the RSU case decision firmware replaces the standard firmware The decision firmware copies have pointers to the follow...

Page 170: ...r Block 1 point to Application Images Decision Firmware Decision Firmware Decision Firmware Decision Firmware PointerBlock 0 PointerBlock 1 Factory Image Application Image 1 Application Image 2 Higher...

Page 171: ...cks contain a list of application images to try until one of them is successful If none is successful the SDM loads the factory image To ensure reliability the pointer block includes a main and a back...

Page 172: ...Example section The decision firmware version must first be queried in U Boot for the value to be available in Linux 5 4 1 3 RSU Image Layout Your Perspective The sub partition table SPT is used for...

Page 173: ...Sub partition Name Contents CPB1 Pointer block 1 P1 Application image 1 P2 Application image 2 5 Remote System Update RSU 683673 2021 10 29 Send Feedback Intel Agilex Configuration User Guide 173...

Page 174: ...on Images BOOT_INFO Factory Image Sub Partition Table 0 Sub Partition Table 1 PointerBlock 0 PointerBlock 1 Application Image 0 Application Image 1 Higher Addresses base Can only be updated through an...

Page 175: ...crease the partition size update the End Address value in the Edit Partition dialog box window as described in the Generating the Initial RSU Image Table 46 RSU Image Sub Partitions Layout Flash Offse...

Page 176: ...us Prime Pro Edition software version 20 4 1 starting with Intel Quartus Prime Pro Edition software version 20 4 0x008 4 Number of entries 0x00C 4 Checksum 0 before Intel Quartus Prime Pro Edition sof...

Page 177: ...e Generator sets these flags as follows at image creation time then they are not changed afterward Table 49 Flags Specifying Contents and Access Partition System Read Only BOOT_INFO 1 1 FACTORY_IMAGE...

Page 178: ...TS A typical configuration pointer block update procedure consists of adding a new pointer and potentially clearing an older pointer Typically the pointer block update uses one additional entry Conseq...

Page 179: ...s to this address If the configuration pointer block runs out of space for new application images the client compresses the pointer block by completing the following actions 1 Read all the valid entri...

Page 180: ...QSPI erase granularity of 32 KB or less When configured with a coarser erase granularity like 64 KB for example the operation fails All supported flash devices offer erase granularities of 4 KB 32 KB...

Page 181: ...y For more information refer to Generating an Application Image When using the HPS to manage RSU both U Boot and LIBRSU clients implement the below procedure to relocate application images targeting a...

Page 182: ...enerate the initial image using the sof file 5 5 1 1 Generating the Initial RSU Image Using sof Files Follow these steps to generate the initial RSU image 1 On the File menu click Programming File Gen...

Page 183: ...page 7 image is the lowest priority 13 For jic files Click Select at the Flash loader select your device family and device name and click OK 14 Click Generate to generate the remote system update prog...

Page 184: ...5 1 2 Generating the Initial RSU Image Using rbf Files Follow these steps to generate the initial RSU image using rbf file 1 Run the following command to generate a rbf file from a factory or applica...

Page 185: ...ry rbf to the FACTORY_IMAGE partition c Assign app1 rbf and app2 rbf to the P1 and P2 respectively Note P1 and P2 are user defined partition names 10 If you generate the jic file select the Flash Load...

Page 186: ...Figure 70 Generating Remote System Update Programming Files 5 Remote System Update RSU 683673 2021 10 29 Intel Agilex Configuration User Guide Send Feedback 186...

Page 187: ...ut Files tab assign the output directory and file name 5 Select the output file type Select the following file types for AS x4 configuration mode Raw Programming File rpd 6 In Intel Quartus Prime soft...

Page 188: ...a third party programmer that does not support the little endian format Set the Bit swap to On to generate the rpd file in big endian format Note The rsu1 tcl script that Intel provides performs the...

Page 189: ...ddress o bitswap ON o rsu_upgrade ON Note The rsu1 tcl script that Intel provides performs the bit swap operation Consequently if you are using this script set bitswap OFF in the command above Alterna...

Page 190: ...typically includes the minimum amount of logic necessary to successfully debug your design if your application image fails to load Consequently the Start address can be the sector boundary of unused s...

Page 191: ...d party programmer that does not support the little endian format set Bit swap to On to generate the rpd file in big endian format Note The rsu1 tcl script that Intel provides performs the bit swap op...

Page 192: ...elect the sof and then click Properties Turn On Generate RSU factory update image Specify the Bootloader file Note You only have to specify the Bootloader file for Intel Agilex SX devices 5 Remote Sys...

Page 193: ...Click Generate to generate the RSU programming files You can now update the Intel Agilex firmware You can save the configuration in a pfg file for later use 5 Remote System Update RSU 683673 2021 10...

Page 194: ..._DEVICE_OP and RSU_IMAGE_UPDATE 4 Close exclusive access to the AS x4 interface QSPI_CLOSE 5 6 Remote System Update from FPGA Core Example This section presents a complete remote system update example...

Page 195: ...e remote system update host controller for your factory and application images In addition your design must include the Reset Release Intel FPGA IP This component holds the design in reset until the e...

Page 196: ...B Connection User Mode Reset User Mode Reset Power On Reset 5 6 2 Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 1 On the File menu click Programming Fi...

Page 197: ...es Tab Creating Initial Flash Image Configuration Mode Raw Programming Data Output Directory Output File Name Device Family JTAG Indirect Configuration Memory Map File map 6 On the Input Files tab cli...

Page 198: ...ick OK 10 Select the MT25QU02G flash memory and click Add Partition 11 In the Add Partition dialog box select Bitstream_2 for the application image sof in the Input file drop down list Assign Page 1 K...

Page 199: ...ND ADDRESS BOOT_INFO 0x00000000 0x0020FFFF FACTORY_IMAGE 0x00210000 0x0048FFFF SPT0 0x00490000 0x00497FFF SPT1 0x00498000 0x0049FFFF CPB0 0x004A0000 0x004A7FFF CPB1 0x004A8000 0x004AFFFF Application I...

Page 200: ...mmer and click Add File Select the generated jic file output_file jic and click Open 2 Turn on the Program Configure for the attached jic file 3 To begin programming the flash memory with the initial...

Page 201: ...ve the current running image address from the remote system update status report The current image address must match the start address for the application image printed in the map file Figure 81 Runn...

Page 202: ...ctory image Figure 82 Verify Current Image Using rsu_status Command source rsu1 tcl channels local top master_1 rsu_status current image address 0x004b0000 first failing image address 0x00000000 faili...

Page 203: ...manage RSU you must update both copies of the Configuration Pointer Block CPB0 and CPB1 and the sub partition table SPT In a non HPS case while updates to both copies of the pointer blocks are mandato...

Page 204: ...new application image Verifying the Update to the New Image Pointer qspi_read 0x004a0028 1 0x02000000 qspi_read 0x004a8028 1 0x02000000 Host software can now reconfigure the Intel Agilex FPGA with th...

Page 205: ...d another new application image in the next or subsequent image pointer entry or allow the device to fall back to the previous or secondary application image in your application image list The followi...

Page 206: ...i_write_one_word 0x002ec028 0x004A8028 You can use a QSPI_read to the image pointer entry at offset 0x28 for CBP0 and CPB1 to verify completion of the QSPI_write_one_word commands Figure 88 Verify the...

Page 207: ...proprietary core image CvP configures the FPGA fabric through the PCI Express PCIe link and is available for Endpoint variants only 683673 2021 10 29 Send Feedback Intel Corporation All rights reserv...

Page 208: ...gnals Optional Monitoring 10k MSEL VCCIO_SDM AS x4 Flash Memory DATA 3 0 DCLK nCS0 PCIe Link Core Image Update via PCIe Link 3 4 Periphery Image jic PCIe Host Core Image rbf 1 2 3 n End Point Core Ima...

Page 209: ...uration scheme that uses the PCIe link to deliver an updated bitstream to a target device after the device enters user mode The periphery images which includes the PCIe link remains active allowing Cv...

Page 210: ...nts performance of its FPGA and semiconductor products to current specifications in accordance with Intel s standard warranty but reserves the right to make changes to any products and services at any...

Page 211: ...ansceivers HBM2 PCIe or EMIF are the reference clocks stable and free running before configuration begins 11 Verify that selected clocks match the frequency setting specified in the Intel Quartus Prim...

Page 212: ...behave can help you understand and debug configuration issues 7 3 Understanding Configuration Status Using quartus_pgm command You can read the device configuration status from the command line direc...

Page 213: ...fter the SDM boot ROM performs device consistency checks Figure 90 Example of an Intel Agilex Configuration Bitstream Structure Firmware Section Firmware section Quartus Prime version dependent Design...

Page 214: ...ut SEUs refer to Intel Agilex SEU Mitigation User Guide Related Information Intel Agilex SEU Mitigation User Guide 7 6 Reading the Unique 64 Bit CHIP ID The Chip ID Intel FPGA IP in each Intel Agilex...

Page 215: ...pin PRESERVE_UNUSED_XCVR_CHANNEL QSF assignment Here are some examples of PRESERVE_UNUSED_XCVR_CHANNEL QSF assignments Global QSF assignment set_global_assignment name PRESERVE_UNUSED_XCVR_CHANNEL ON...

Page 216: ...LK_1 select the Internal Oscillator option in the Intel Quartus Prime Try configuring the Intel Agilex device with a simple design that does not contain any IP If configuration via a non JTAG scheme f...

Page 217: ...Intel Corporation All rights reserved Intel the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries Intel warrants performance of its FPGA and semiconductor produc...

Page 218: ...al Non Volatile Flash Memory in the following figures Connections for Avalon ST x8 Single Device Configuration Connections for Avalon ST x16 Single Device Configuration Connections for Avalon ST x32 S...

Page 219: ...note in the Reconfiguration Timing section Re ordered sections for clarity Revised Intel Agilex Configuration Flow Diagram section Renamed Power Up section to Power On to align the description with f...

Page 220: ...nfiguration scheme Added new topic Firmware Version Information Clarified usage of Use relative address option in the Application Image Layout and Generating an Application Image sections Added new vi...

Page 221: ...ommended Design Constraints for Using CFI Flash Added new QSPI flash recommendation for PCIe designs in the AS Configuration Scheme Hardware Components and File Types section Revised Debugging Guideli...

Page 222: ...Updated AS Configuration Added text describing QSPI flash reset Removed 108 MHz support from the Supported configuration clock source and AS_CLK Frequencies in Intel Agilex Devices table Updated AS_C...

Page 223: ...the Command List and Description table The text specifies that the maximum transfer size is 4 kilobytes or 1024 words Updated note in the Adding an Application Image The note states When using HPS to...

Page 224: ...SM firmware provides SEU single bit error and double adjacent bit error detection and correction The multi bit error and non adjacent bit error are detected but cannot be corrected 2020 06 30 20 2 Mad...

Page 225: ...as don t care if POR doesn t meet the specified time Updated Intel Agilex Configuration Flow Diagram Revised the Intel Agilex FPGA Configuration Flow diagram Revised Power Up section Added text in the...

Page 226: ...d command to save the programming file Removed guidelines related to SD MMC device configuration in the following sections Removed SD MMC flash memories support in the Intel Agilex Configuration Overv...

Page 227: ...Data Width Clock Rates and Data Rates Intel Agilex support x8 and x16 CvP for the Gen3 and Gen4 data rates 2019 12 16 19 4 Made the following changes Added a new chapter covering the Reset Release Int...

Page 228: ...reater than 125 C Added the an eighth word to the to the RSU_STATUS response Word 8 Current image retry counter Added new field to the 5th word of the RSU_STATUS response This field specifies the sour...

Page 229: ...yout CMF Pointer Block Layout Modifying the List of Application Images Application Image Layout Command Sequence To Perform Quad SPI Operations The static firmware has been replaced by decision CMF Th...

Page 230: ...he device reverts to the MSEL specified boot source nSTATUS must be stable during JTAG configuration In both sentence nSTATUS should be nCONFIG Removed pin assignments for CVP_CONFDONE for the Avalon...

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