3. Power Up the Development Kit
This chapter describes how to apply power to the development board and provides
default switch and jumper settings.
3.1. Default Settings
The Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit ships with its board
switches preconfigured to support the design examples in the kit. If you suspect your
board might not be correctly configured with the default settings, follow the
instructions in the table below to return to its factory settings before proceeding.
Table 4.
Factory Default Switch Settings
Switch
Default Position
Function
SW1[1:4]
ON/OFF/OFF/OFF
PCIe PRSNT x1/x4/x8/x16 settings switches. Default = x16.
PRSNT x16
PRSNT x8
PRSNT x4
PRSNT x1
ON
OFF
OFF
OFF
SW2
ON
Intel FPGA Download Cable II JTAG Selection switch. Default ON selects
the micro-USB port on-board blaster for FPGA programming.
SW3[1:4]
ON/ON/ON/OFF
Configuration mode selection, BMC JTAG selection, and HPS JTAG Bypass
switches.
SW3[1:2]
—Configuration mode selection.
MSEL0
is pulled high. Default
mode is AS x4.
Mode
SW3[1]
-
MSEL1
SW3[2]
-
MSEL2
JTAG
OFF
OFF
Avalon-ST x16
ON
OFF
AS x4 (Fast)
ON
ON
SW3[3]
—BMC JTAG selection.
• ON selects the on-board blaster as JTAG master when no external
blaster is plugged
• OFF selects the PCIe RP as JTAG master when no external blaster is
plugged
• Default JTAG chain selects the FPGA
SW4[4]
—HPS JTAG Enable.
• ON enables the HPS as part of the JTAG chain
• OFF bypasses the HPS from the JTAG chain
• The HPS is set to bypass by default
SW4[1:4]
OFF/OFF/OFF/OFF
Clock features selection switches.
continued...
739942 | 2022.09.21
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