Intel AGIB027R29A1E2VR0 User Manual Download Page 53

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Figure 39.

Power Tree Diagram

VCC_HSSI_GXF_EN

VCC_HSSI_GXR_EN

VCCE_PLL_EN

VCCERT_FGT_GXF_EN

3p3V_EN

IO_1p8V_EN

VCCRT_GXR_EN

1p2V_DDR4_CH2_EN

2p5V_EN

1p2V_DDR4_CH01_EN

VCCED_GXR_EN

1p8V_EN

VCCCLK_GXR_EN

VCCR_CORE_EN

FPGA_VCC_EN

VCCH_EN

IO_3p3V_EN

VTT_DDR4_Ch2_EN

VTT_DDR4_CH01_EN

VCCFUSEWR_SDM_EN

VCCPT (4.38A)

VCCL_HPS / VCCH_SDM

VCCPLLDIG_HPS (0.02A)

VCCH_FGT_GXFL_12A (2.62A)

VCCCLK_GXFL (6.4mA)

VCCH (8.1A)

VCC_HSSI_GXRL14C/15A/15C

(25.43A)

VCCA_PLL (6.9A)

VCCR_CORE (9.1A)

VCCRT_GXRR_15A/15C

VCCRT_GXRL_14C

1p2V_PRE

1p8V_PRE

2p5V_PRE

3p3V_STBY

VCCERT_FGT_GXFL_12A (6.72A)

VCC_HSSI_GXF_12A (17.26A)

VCCL_SDM (0.39A)

DDR-T

12V

17.26A

1.8V
1p8V

1.8V

IO_1p8V

1p8V_VCCCLK_GXF

1p8V_VCCH_GXR

VCCH_FGT_GXF

1p8V_FLTR

0p9V_VCC_HSSI_GXR

0p9V_VCCL_HPS

0p9V_VCCED_GXR

0p8V_VCCH

1p0V_VCCFUSE_GXR

1p0V_VCCCLK_GXR

VCCFUSEWR_GXF

1p2V_DDR4_CH01

1p8V_VCCIO_EN

3.3V

0.5A

3.0A

1p2V_DDR4_CH2_EN

VTT_DDR4_CH2_EN

2p5V_EN

0p6V_VREF_DDR4_CH2

0p6V_VTT_DDR4_CH2

VCCIO_PIO_3A/3B/3C/3D

1p2V_DDR4_CH2

1.2V

0.6V

EN63A0QI

0.6V

EN_12V_G1G2_L

12V_GROUP2

12V_GROUP1

PWR ON/OFF

Switch

(For bench use)

EN_SEQ

12V_GROUP1

5.4A

U49

U44

12V_GROUP2

65W(5.4A) PCIe Slot

150W PCIe (12.5A) or

240W (20A) Ext Pwr Adapter

U50

Q13

12V_G1

12V

U45

0.9V

RevB=0.9V

RevA=0.95V

RevA -1.8V

(Group 2)

RevB - 1.2V

Group 3)

RevB=0.8V

RevA = 0.9V

0.8V/0.9V

VCC_HSSI_GXF_EN

4-phase

0.8V

1.0V

FPGA_VCC_EN

12V

VCCERT_GXF_EN

VCCH_EN

VCC_HSSI_GXR_EN

VCCFUSEWR_SDM_EN

VCCL_HPS_EN

1.0V

2.5V

LDO

POWER_ON

Power ON/OFF

Circuit

MAX10

PWR SEQ

LTC4357

Ideal Diode

Ctlr U51

12V

PCIe Slot

Edge Conn

LTM4625

U61

LTC4365

Selew Rate

Ctlr

EM2130H

U64

LTC4365

Selew Rate

Ctlr

ED8401

+ET6160 x4

U56,U57,U58,U60

EM2120L

U72

LTC7151S

U68

LTC4357

Ideal Diode

Ctlr

12V

ATX 2x4

Pwr Conn

LTC4359

Ideal Diode

Ctlr U48

POWER_ON

12V_G2

3p3V_EN

IO_3p3V_EN

LTC4365

Selew Rate

Ctlr

0.02A

FB29

VCC (174A) / VCCP (21.34A)

VCCPLLDIG_SDM (0.02A)

VCCRT_FGT_GXF_EN

VCCR_CORE

VCCE_PLL_EN

VCCE_PLL_DTS_GXR

2p5V

VTT_DDR4_CH01_EN

0p6V_VREF_DDR4_CH01

0p6V_VTT_DDR4_CH01

0.6V

U83

UB4

J11

SW6

0.6V

1.0V 0.3A

1.0V 1.5A

1.0V 0.3A

FB31

FB1

FB26

VCCR_CORE

VCCA_PLL_FLTR

FB30

FB32

FB33

DNI

1.2V

U87

5.4A ( 2.7A x2)

IO_3p3V

3.3V

3p3V_STBY

1.2V

1p2V_PRE

1.8V

2.5V

12.28A

1p0V_VCCRT_GXR

RevA -Use EM2120H

1.0V

1.2V/1.8V

1p8V_PRE

2p5V_PRE

2.4V

1.0V

LDO

Buck
LDO

1.0V
1.0V

0 12V/5V/1p8V_PRE/3p3V_STBY/1p2V_PRE/2p5V_PRE

1 Group1

2 Group2

3 Group3

Board Power on

Power Sequence Start

Power-up Sequence: (No power down sequence requirment)

FLTR

Max 10W Class 5

QSFPDD0_VCC/QSFPDD0_VCCT/QSFPDD0_VCCR

QSFPDD1_VCC/QSFPDD1_VCCT/QSFPDD1_VCCR

VCCH_GXRL_14C/15A/15C

(0.4A)

VCCFUSEWR_GXFL_12A (<1mA)/

VCCFUSECORE_GXFL_12A

VCCCLK_GXR

(VCCN1V_IO_GXR) (0.92A)

VCCHFUSE_GXR (0.15A)

VCCIO_SDM (1mA)

VCCIO_HPS (0.19A)

VCCBAT (0.012mA)

VCCIO_PIO_2B/2E/2F/2C

1p2V_DDR4_CH01

VCCED_GXR_EN

1p8V_EN

3.3V

VCCCLK_GXR_EN

VCCFUSEWR_SDM (1mA)

EN63A0QI

LT3042

U81

EN6337QI

U86

U88

U52

U46

U47

U82

U75

EZ6301QI

3-output

U89

2p5V

VCCE_PLL_GXRL

(1.3mA)

VCCE_DTS_GXRL

(1.0mA)

EP53F8QI

U62

EP53F8QI

U79

EP53F8QI

U77

VCCADC (0.014A)

VCCPLL_SDM/ VCCPLL_HPS

(5mA/1mA)

LTC7151S

U69

EP53F8QI

U63

LTM4657

U67

LTM4657

U66

EN63A0

U73

LT7151S

U71

EM2140L

U70

12V

VCCED_GXR (2.55A)

EM2120L

U65

1p2V_DDR4_
CH01_EN

EP53F8QI

U80

EN6347QI

TPS51200

U84

U85

U75

A.13.3. Power Sequence

Intel Agilex FPGA requires proper power-up sequencing.

For more details on the power sequencing groups, refer to Table: Voltage Rails Group

in the

Intel Agilex Power Management User Guide

For more information on the connection guidelines, refer to the

Intel Agilex Device

Family Pin Connection Guidelines

A. Development Kits Components

683288 | 2022.09.22

Send Feedback

Intel

Agilex

™

I-Series FPGA Development Kit User Guide

Summary of Contents for AGIB027R29A1E2VR0

Page 1: ...Intel Agilex I Series FPGA Development Kit User Guide Online Version Send Feedback UG 20338 ID 683288 Version 2022 09 22...

Page 2: ...ing Environment 22 4 1 1 Download OpenJDK 23 4 1 2 Download OpenJFX 23 4 1 3 Install OpenJDK and OpenJFX 24 4 1 4 Run BTS GUI 24 4 2 Test the Functionality of the Development Kit 25 4 2 1 The Bottom I...

Page 3: ...wer Measurement 54 A 14 Temperature Monitoring 55 A 15 Mechanical Requirements 55 A 16 Board Thermal Requirements 56 A 17 Board Operating Conditions 57 A 18 Over Temperature Warning LED 57 B Additiona...

Page 4: ...and receive CXL soft R Tile Wrapper and Soft Support logic purchase or activation of a separate CXL IP license is required for proper use with the Intel Quartus Prime Design Software Contact your loc...

Page 5: ...with ECC Comp CH1 DDR4 x72 with ECC 12A F Tile x20 GPIO 3A 3B 3C 3D HPS USB PHY Feature Summary Intel Agilex I Series AGIB027 device in the 2957A BGA package 0 8 VID adjustable VCC core R tile transce...

Page 6: ...ons switches and LEDs System reset push button CPU reset push button PCIe reset push button Four dedicated user LEDs Link LED of each QSFP28 port to indicate the link and data transceiver Two dedicate...

Page 7: ...0 C to 35 C Maximum ICC load current 198 A Maximum ICC load transient percentage 30 Maximum FPGA power supported by the supplied heatsink fan 180 W Handling Precautions When handling the board observ...

Page 8: ...rtus Prime Standard Edition or Intel Quartus Prime Pro Edition you can use that license file with this kit If not follow these steps 1 Log on at the My Intel Account Sign In web page and click Sign In...

Page 9: ...e board before shipment Use this data to restore the board with its original factory content Related Information Intel Agilex I Series FPGA Development Kit 2 3 Installing the Intel FPGA Download Cable...

Page 10: ...can be damaged by power supplies with greater voltage 2 Set the power switch SW6 to the ON position When the board powers up the blue power LED illuminates and the board is ready for use The blue LED...

Page 11: ...1 Switch Default Position Function SW1 1 4 ON OFF OFF OFF PCIe PRSNT x1 x4 x8 x16 settings Default x16 PCIe PRSNT x16 PCIe PRSNT x8 PCIe PRSNT x4 PCIe PRSNT x1 ON OFF OFF OFF SW2 1 4 ON OFF OFF X Conf...

Page 12: ...JTAG Select Intel MAX 10 JTAG Enable Intel MAX 10 JTAG Disable 4 Not used X X SW6 ON OFF When the board is not in a PCIe slot it must be powered by an external power supply The SW6 switch turns on the...

Page 13: ...ure 4 SW2 1 4 Switch Setting Figure 5 SW3 1 4 Switch Setting Figure 6 SW4 Switch Setting 3 Development Board Setup 683288 2022 09 22 Send Feedback Intel Agilex I Series FPGA Development Kit User Guide...

Page 14: ...DRT Dual DIMM A J2 DIMM B connector DDR4 DDRT Dual DIMM B J5 PCIe x16 Gold Finger J6 J7 CXL PCIe connectors For connecting the external CXL PCIe MCIO cables J24 Fan connector For connecting to the hea...

Page 15: ...tem Intel MAX 10 pre programmed If you want to restore board QSPI flash with factory default image follow these steps 1 Connect the USB cable between J8 USB connector and your computer 2 Open Intel Qu...

Page 16: ...b to specify a sof that contains the configuration bitstream 6 Click on the Configuration Device Add Device to specify the flash device In the Device list of the pop up window select CFI_2Gb for the c...

Page 17: ...e to generate the pof file 3 4 How to Program the Generated POF Image To program the generated POF image follow these steps 1 Plug in the USB cable to the USB port J8 or J10 when using J10 DIPSWITCH S...

Page 18: ...to Detect to scan the JTAG devices 7 Right click the VTAP10 device Edit Change Device change it to MAX 10 10M50DAF256 3 Development Board Setup 683288 2022 09 22 Intel Agilex I Series FPGA Development...

Page 19: ...vice select Quad SPI Flash Memory QSPI_2Gb 9 In the Programmer page click QSPI_2Gb Change File to select the pof file 10 Start the Programmer 3 Development Board Setup 683288 2022 09 22 Send Feedback...

Page 20: ...FPGA development kit to configure successfully Before you add the following SmartVID setting into the Quartus settings file qsf you must change the configuration scheme to Avalon streaming interface x...

Page 21: ...nment name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE...

Page 22: ...oad and install Java runtime including OpenJDK and OpenJFX on your systems and set up the running environment This is a one time procedure so if you have already completed it before you do not need to...

Page 23: ...se the JRE tar gz format file Note The JDK version can be updated download the latest version 4 1 2 Download OpenJFX To download the OpenJFX follow these steps 1 Download the OpenJFX using this link h...

Page 24: ...the files and rename the folders using the following commands unzip openjfx 17 0 2_linux x64_bin sdk zip d opt Java tar zxvf OpenJDK11U jre_x64_linux_hotspot_11 0 15_10 tar gz C opt Java cd opt Java...

Page 25: ...f the board is connected to the system The green sign turns gray if the board becomes disconnected Intel Quartus Prime Version Displays the current Intel Quartus Prime version installed and active on...

Page 26: ...3 When configuration finishes the design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled If you use the Intel Quartus Prime Programmer...

Page 27: ...in The JTAG chain control shows all the devices currently in the JTAG chain Note Change the settings of SW5 to bypass or enable power for Intel MAX 10 and Intel Agilex FPGA System Intel MAX 10 and FPG...

Page 28: ...Access Over MAX10 allows you to read and write the data at the address you specify Qsys Memory Map The Qsys Memory Map control shows the memory map of bts_config sof design running on your board 4 2 5...

Page 29: ...d or unlocked state Pattern Sync Shows the pattern synced or not state The pattern is considered synced when the start of the data sequence is detected Detail Shows the PLL lock and pattern sync statu...

Page 30: ...he transmitter buffer Post tap 1 Specifies the amount of pre emphasis on the post tap of the transmitter buffer Figure 20 QSFPDD PMA Setting Data Type The Data Type control specifies the type of data...

Page 31: ...ansmit data stream each time you click the button Insert error is only enabled during transaction performance analysis Clear Resets the Detected Errors counter and Inserted Errors counter to zeros Run...

Page 32: ...F tile performance the QSFPDD0 only reserves 4 channels 4 2 6 The RAM Tab This tab allows you to read and write DDR4 COMP0 DDR4 COMP1 and DDR4 RDIMM memory on your board Download DDR4 designs through...

Page 33: ...hieve Write MBps and Read MBps Show the number of bytes analyzed per second Data Bus 72 bits 8 bits ECC wide reference clock is 100 MHz and the frequency is 1066 MHz double data rate 2133 MT s Test Co...

Page 34: ...Bit Error Rate Calculates the bit error rate of the transmit data stream Insert Insert a one word error into the transaction stream each time you click the button Insert error is only enabled during t...

Page 35: ...lso be started with the BTS GUI icon Clock The Clock Controller communicates with the System Intel MAX 10 device through either USB port J8 or 10 pin JTAG header J10 Then System Intel MAX 10 controls...

Page 36: ...1 to update the settings of the NVM Register changes are volatile after power cycling Clockbuilder Pro Software on Skyworks website 4 4 Monitor On board Power Regulator through Power Monitor GUI The P...

Page 37: ...mp R Tile 15C Temp R Tile 15A Temp FPGA die internal temperature sense diodes 4 5 BTS Test Areas BTS checks for hardware fault before you can use the board If one or more BTS test items fail it implie...

Page 38: ...Plug QSFPDD0 QSFPDD1 loopback module in J3 J4 before you configure QSFPDD NRZ example build through BTS GUI 4 Board Test System 683288 2022 09 22 Intel Agilex I Series FPGA Development Kit User Guide...

Page 39: ...pdated Figure Windows Console Updated Figure Linux Console Updated Figure The Configure Menu Updated Figure The Sys Info Tab Updated Figure The QSFPDD NRZ Tab Updated Figure QSFPDD PMA Setting Updated...

Page 40: ...ing Added Figure SW5 1 4 Switch Setting Updated the PCIe and CXL Interfaces section Updated Figure Intel Agilex I Series FPGA Development Board Image Front Updated the header of Table Intel Agilex I S...

Page 41: ...back Intel Corporation All rights reserved Intel the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries Intel warrants performance of its FPGA and semiconductor p...

Page 42: ...ceive CXL soft R Tile Wrapper and Soft Support logic purchase or activation of a separate CXL IP license is required for proper use with the Intel Quartus Prime Design Software Contact your local Inte...

Page 43: ...Figure 30 MCIO Connector J7 J6 MCIO Connectors for CXL PCIe Interface A Development Kits Components 683288 2022 09 22 Send Feedback Intel Agilex I Series FPGA Development Kit User Guide 43...

Page 44: ...2HR K64129 002 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 MH1 MH3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12...

Page 45: ...28 Gbps NRZ and 325 50 MHz clocks for the 56 Gbps PAM4 These clocks must have RPM jitter 250fs Figure 32 F Tile Bank 12A Circuit A 7 Port Controller A Texas Instrument FPC202 dual port controller ser...

Page 46: ...26 48 49 56 55 2 1 3 5 4 6 7 17 18 11 13 10 12 14 16 15 50 47 46 IO_3p3V R133 4 70k 0402 1 R132 4 70k 0402 1 C304 0 1uF 0402 25V X6S C303 1uF 0402 25V X6S C302 0 1uF 0402 25V X6S C300 0 1uF 0402 25V...

Page 47: ...faces to the Intel Agilex FPGA in the AVST x8 mode The Intel MAX 10 also interfaces to the QSPI flash in the active serial AS x4 mode For the AS x4 mode MSEL 2 0 configuration pin strapping SW2 must b...

Page 48: ...supported Two independent on board DDR4 and one dual DIMM sockets for DDR4 or DDR T The on board DDR4 uses five 16Gb DDR4 single rank devices connecting to Bank 2B 2E for memory component channel 0 an...

Page 49: ...42 EM2140P 0x45 EM2120L 0x46 EM2120L I2C2 0x1E FPC202 0x57 0x5F M24128 0x38 MAX31730 0x3A MAX31730 0xA0 QSFPDD_0 0xA0 QSFPDD_1 I2C3 0xA0 DDR4_DIMM0 PCIE_EP_3V3_I2C 0xA2 DDR4_DIMM1 Intel MAX 10 I2C Add...

Page 50: ...re 36 Clock Connection Diagram 2B 2E 2F 2C 3A SDM 12A F Tile 14C R Tile Si53307 Mux_buffer 15C R Tile 3B 3C 3D Intel Agilex FPGA CXL CONN Si510 Si52204 Outputs x4 Si5391 Outputs x12 Intel MAX 10 Downl...

Page 51: ...this mode plug the board into an available PCI Express slot and connect the standard 2x4 power cords available from the PC s ATX power supply to J11 on the board The PCIe slot together with the auxili...

Page 52: ...ply A 13 2 Power Distribution System The following figure below shows the power distribution system on the Intel Agilex I Series FPGA development board A Development Kits Components 683288 2022 09 22...

Page 53: ...48 POWER_ON 12V_G2 3p3V_EN IO_3p3V_EN LTC4365 Selew Rate Ctlr 0 02A FB29 VCC 174A VCCP 21 34A VCCPLLDIG_SDM 0 02A VCCRT_FGT_GXF_EN VCCR_CORE VCCE_PLL_EN VCCE_PLL_DTS_GXR 2p5V VTT_DDR4_CH01_EN 0p6V_VRE...

Page 54: ...AT VCCFUSEWR_SDM IO_3p3V QSFPDD0_VCC VCCT VCCR QSFPDD1_VCC VCCT VCCR 1p2V_DDR4_CH01 1p2V_DDR4_CH02 0p6V_VREF_DDR4_CH01 0p6V_VREF_DDR4_CH02 0p6V_VTT_DDR4_CH01 0p6V_VTT_DDR4_CH02 VCCPIO VCCR_CORE VCCA_P...

Page 55: ...ard Temperature Measurement Circuit DXP1 EU1 DXN1 DXP2 DXN2 DXP3 DXN3 SDA SCL VDD 1 2 3 4 5 6 7 11 12 9 10 8 13 3p3V_STBY 3p3V_STBY THERM ADD GND GND_EP MAX31730ATC C570 0 1 F I2C ADDR 3A TEMP2_THERMn...

Page 56: ...signed to cool up to 250W total power of the board An active cooling design is used The heatsink is designed to meet the height constraints of a 2 slot PCIe card form factor as defined by the PCIe CEM...

Page 57: ...ing Conditions Operating Condition Range Maximum power dissipation 250W Maximum ambient temperature 0 C to 35 C FPGA junction temperature 85 C A 18 Over Temperature Warning LED A red colored LED D9 is...

Page 58: ...tle 47 the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47 Safety Assessment an...

Page 59: ...emove all DC power from the board system The socket outlet must be installed near the equipment and must be readily accessible System Grounding Earthing To avoid shock you must ensure that the power c...

Page 60: ...tenance of this product during an electrical storm Risk of Fire To reduce the risk of fire keep all flammable materials a safe distance away from the boards and power supply You must configure the dev...

Page 61: ...interference to radio communications If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment on and off you are required to...

Page 62: ...e Risk of fire explosion or chemical burn if the battery is mistreated punctured or crushed Do not attempt to disassemble Do not incinerate Observe proper polarity when replacing battery Do not dispos...

Page 63: ...tandards mandated by Directive 2014 30 EU Because of the nature of programmable logic devices it is possible for the user to modify the development kit in such a way as to generate electromagnetic int...

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