82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
14
Note:
To use this configuration for the 82562EZ(EX) Platform LAN Connect device, be sure the AND
gate U1 is populated. Depopulate the 0
Ω
resistor R2.
Figure 4. 82541xx LAN Disable Circuitry
3.3.2
Serial EEPROM for 82541xx Controller Implementations
82541xx Gigabit Ethernet Controllers can use either a Microwire* or an SPI* serial EEPROM. The
EEPROM mode is selected on the EEMODE input (pin J4). A pull-up resistor to V
cc
denotes an
SPI* EEPROM (82541GI/EI only). A pull-down resistor to ground denotes a Microwire
EEPROM. Several words of the EEPROM are accessed automatically by the device after reset to
provide pre-boot configuration data before it is accessed by host software. The remainder of the
EEPROM space is available to software for storing the MAC address, serial numbers, and
additional information.
For non-ASF applications, a 64 register by 16-bit Microwire serial EEPROM should be used, and
for ASF 1.0 applications, a larger 93C66 Microwire or AT25040 SPI* serial EEPROM. ASF 2.0
requires an 8 KB SPI* serial EEPROM.
Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program
EEPROM images in development or production line environments. To obtain a copy of this
program, contact your Intel representative.
IO
Control
Hub 5
Super IO
Chip
82541(PI/GI(EI)
82540EP
RST#
RST# (B9)
RSM_RST#
R1
10 K
R2
0 Ohm
Pop = Y
LAN_PWR_GOOD
(A9)
82562EZ(EX) Disable Circuit
U1
FLSH_SO
(P9)
Pop = Y means populate this option
