Intel 82541PI, Design Manual

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82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Application Note (AP-468) 21
3.6.9 Oscillators for 82541PI Controllers
The 82541PI clock input circuit is optimized for use with an external crystal. However, an
oscillator may also be used in place of the crystal with the proper design considerations (see
Table 17 ):
•
The clock oscillator has an internal voltage regulator of 1.2 V to isolate it from the external
noise of other circuits to minimize jitter. If an external clock is used, this imposes a maximum
input clock amplitude of 1.2 V.
•
The input capacitance introduced by the 82541PI (approximately 20 pF) is greater than the
capacitance specified by a typical oscillator (approximately 15 pF).
•
The input clock jitter from the oscillator can impact the 82541PI clock and its performance.
Table 15. Electrical Specifications at 25
°
C for 1000 Gb Silicon
Insertion Loss (TX / RX)
0.1 through 999 kHz 1.0 dB maximum
1.0 through 60.0 MHz 0.6 dB maximum
60.1 through 80.0 MHz 0.8 dB maximum
80.1 through 100.0 MHz 1.0 dB maximum
100 through 125.0 MHz 2.4 dB maximum
Return Loss (TX / RX)
1.0 through 40.0 MHz 18 dB minimum
40.1 through 100 MHZ 12 - [20Log(f/80 MHz)] dB minimum
Common Mode-to-Common Mode Rejection
1.0 through 60 MHz 48 dB minimum
60.1 through 100 MHz 42 dB minimum
100.1 through 150 MHz 37 dB minimum
Differential-to-Common Mode Rejection
1.0 through 60 MHz 35 dB minimum
60.1 through 100 MHz 29 dB minimum
100.1 through 150 MHz 22 dB minimum
Crosstalk Isolation (TX / RX)
1.0 through 80 MHz 36 dB minimum
80.1 through 150 MHz 27dB minimum
High Voltage Isolation
1500 Vrms minimum, at 50 to 60 Hz, for 60 sec. 2250 V dc for 60 seconds
OCL with 8 mA Bias 400 uH minimum