Intel
®
81341 and 81342 I/O Processors
December 2007
Developer’s Manual
Order Number: 315037-002US
683
SRAM Memory Controller—Intel
®
81341 and 81342
8.3.3
Error Correction and Detection
The SMCU is capable of correcting any single bit errors and detecting any double bit
errors in the 81341 and 81342 SRAM memory subsystem. ECC enhances the reliability
of a memory subsystem by correcting single bit errors caused by electrical noise or
occasional alpha particle hits on the SRAM memory array.
Similar to parity, which simply detects single bit errors, error correction requires an
additional 7-bit code word for the 32-bit datum. The 81341 and 81342 implements a
256-bit data path to the SRAM array, but a 7-bit error correction code per every 32-bit
datum. For example,
SCB0[6:0]
for
DQ[31:0]
,
SCB1[6:0]
for
DQ[63:32]
,
SCB2[6:0]
for
DQ[95:64]
and so on, resulting in a 312-bit wide memory subsystem.
During SRAM read cycles, the SRAM Control Block detects single bit errors and corrects
the data prior to returning the data to the respective memory transaction queue. SRAM
write cycles generate the ECC and sends it with the data to the memories.
Scrubbing is the process of correcting an error in the memory array. The chance of an
unrecoverable multi-bit error increases if the software does not correct a single-bit
error in the array. For the 81341 and 81342, scrubbing is handled by software. If error
reporting is enabled, the SMCU logs the error type in SELOG and the address in SECAR
and SECUAR when an error occurs.
