Intel
®
81341 and 81342—DDR SDRAM Memory Controller
Intel
®
81341 and 81342 I/O Processors
Developer’s Manual
December 2007
588
Order Number: 315037-002US
7.3.3.4
32-bit Data Bus Width
Using 512 Mbit (with x16 devices) SDRAMs, a 64-bit data bus yields a minimum
memory size of 256 MBytes. To address cost-sensitive applications requiring less than
256 MBytes of local memory, the DMCU supports a 32-bit data bus. While 32-bit mode
decreases the minimum memory size to 128 MBytes, the bus throughput is also
reduced to half the throughput of 64-bit mode. For example, the throughput for DDR2
400 in 64-bit mode and 32-bit mode is 3200 MBytes/s and 1600 MBytes/s respectively.
The DMCU does not support switching between 32-bit data bus width and 64-bit data
bus width
.
The data bus width is selected by bit 2 of the SDCR0 (see
Control Register 0 — SDCR0” on page 628
). The default is 64-bit bus width.
Reducing the data bus width by half also reduces the page size by half. Therefore, the
page size is 4 Kbytes for 32-bit data bus versus 8 Kbytes for 64-bit data bus width.
Figure 83. 64-bit to 32-bit Addressing
Data 0
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 9
Data 8
Data 7
Data 0
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 9
Data 8
Data 7
00H
08H
10H
18H
20H
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
Address for
Address for
9
8
7
6
5
4
3
2
1
0
SDRAM Column
Address on MA[13:0]
64-bit Data
32-bit Data
Example assumes that the 32-bit
address in question has the same
row address independent of
memory bus width.
B6257-01
