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Intel® 80331 I/O Processor

Design Guide

Memory Controller

Table 40.

Clock Signal Group Registered/Unbuffered DIMM Routing Requirements

Parameter

Routing Guideline

Reference Plane

Preferred Topology

Route over unbroken ground plane

Differential Microstrip (preferred) or differential
stripline

Preferred Topology

Stripline routing is recommended for the clock signals.
Micro-strip is also acceptable with strict adherence to
all routing recommendations.

Breakout trace width and spacing

5 mils x 5 mils routed as differential pair

Microstrip Trace Width

Differential: Trace impedance of 100 ohms

Refer to

Figure 41

Trace Spacing (edge to edge)

5 mils for breakout

5 mils from one clock M_CK of the differential pair
M_CK#.

>20 mils between the other signals or vias including
other clock pairs.

Package Trace Length

Breakout Trace Length (TL1)

Lead-in to Connector Length (TL2)

See

Table 37

for the net length details.

<= .5”

2.0” to 10” (correlated /- 1.0” of DQ/DQS and
command trace lengths)

Termination:

- Buffered Termination

- Un-Buffered Termination

None required

22.1 ohms +/- 5% series termination on each
differential segment after the breakout.

Length matching Requirements:

The package lengths from Die to Ball provided in

Table 37

must be accounted for when length matching

•

Within differential clock pairs

•

+/- 0.025” max. within Pairs [Intra-pair]

•

With respect to the DQ/DQS group (from die to
DIMM connector)

•

+/- 1.5” max. when M_CK is routed Stripline

•

+/- 1.0” max. when M_CK is routed Micro-strip

•

With respect to Address/Command group (from
die to DIMM connector)

•

For total capacitive loads greater than 36pF,
M_CK trace lengths must be 2.0” to 3.0” longer
than all ADD/CMD/CTRL trace lengths

•

For capacitive loads less than or equal to 36pF,
M_CK trace lengths must be 1.0” to 3.0” longer
than all ADD/CMD/CTRL trace lengths

•

Among Unbuffered Clock Pairs

•

+/- 0.1” max. between the 3 pairs of Unbuffered
Clocks

Series Resistor Rs

•

22.1 +/- 5% ohms unbuffered

•

no series resistor required for registered DIMM’s

Parallel Resistor Rp

•

no parallel resistor required

Routing Guideline 1

Clock signals’ polarity needs to be alternated.

Routing Guideline 2

Maximum of 2 pair of vias from controller to DIMM

Routing Guideline 3

Route clock as differential impedance of 100 ohms
with single ended impedance of 50 ohms

Summary of Contents for 80331

Page 1: ...Intel 80331 I O Processor Design Guide March 2005 Order Number 273823 003 ...

Page 2: ...obtained by calling1 800 548 4725 or by visiting Intel s website at http www intel com AlertVIEW AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips CT Connect CT Media Dialogic DM3 EtherExpress ETOX FlashFile i386 i486 i960 iCOMP InstantIP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel Create Share Intel GigaBlade Intel InBusiness Intel Inside Intel Ins...

Page 3: ...Up Information 37 5 2 Adapter Card Stackup 39 6 PCI X Layout Guidelines 41 6 1 Interrupt Routing and IDSEL Lines 41 6 1 1 PCI Arbitration 42 6 1 2 PCI Resistor Compensation 42 6 2 PCI General Layout Guidelines 43 6 3 PCI X Topology Layout Guidelines 43 6 4 Intel 80331 I O Processor PCI X Layout Analysis 44 6 4 1 PCI Clock Layout Guidelines 45 6 4 2 Single Slot at 133 MHz 48 6 4 3 Embedded PCI X 13...

Page 4: ... Layout Guidelines 101 7 5 1 Simulation Conditions 102 7 5 2 DDRII 400 Trace Width Impedance Requirements 103 7 5 3 DIMM Layout Design 104 7 5 3 1 DDR II 400 DIMM Source Synchronous Routing 104 7 5 3 2 DDRII 400 Clock Routing Guidelines 107 7 5 3 3 DDRII 400 Address Command Control Routing Guidelines 108 7 5 4 Embedded Configuration 110 7 5 4 1 DDRII 400 Embedded Source Synchronous Routine Guideli...

Page 5: ...bug 139 11 1 Requirements 139 11 2 JTAG Signals Header 140 11 3 System Requirements 141 11 4 JTAG Hardware Requirements 142 11 4 1 Macraigor Raven and WindRiver Systems visionPROBE visionICE 142 11 4 2 ARM Multi ICE 142 12 Debug Connectors and Logic Analyzer Connectivity 143 12 1 Probing PCI X Signals 143 13 References 147 13 1 Related Documents 147 13 2 Electronic Information 148 ...

Page 6: ...Slot PCI X 100 MHz Slot Routing Topology 53 23 Embedded PCI X 100 MHz Routing Topology 54 24 Combination of Slot and Embedded PCI X 100 MHz Routing Topology 55 25 Combination of Slots and Embedded PCI X 100 MHz Routing Topology 56 26 PCI X 66 MHz Slot Routing Topology 57 27 PCI X 66 MHz Embedded Routing Topology 58 28 PCI X 66 MHz Mixed Mode Routing Topology 59 29 PCI 66 MHz Topology 60 30 PCI 66 ...

Page 7: ... 400 Embedded Address Control Topology With Split Termination 119 60 Routing Termination Resistors top view 120 61 DDR VREF Circuit 121 62 Data Width and Low Order Address Lines 124 63 Four MByte Flash Memory System 125 64 Peripheral Bus Unlatched Bidirectional Single Load Topology 127 65 Peripheral Bus Latched Bidirectional Single Load Topology 128 66 Peripheral Bus Latched Bidirectional Two Load...

Page 8: ... Mixed Mode Routing Recommendations 59 21 PCI 66 MHz Slot Table 60 22 PCI 66 MHz Embedded Table 61 23 PCI 66 MHz Mixed Mode Table 62 24 PCI 33 MHz Slot Routing Recommendations 63 25 PCI 33 MHz Embedded Routing Recommendations 64 26 PCI 33 MHz Mixed Mode Routing Recommendations 65 27 DDR Bias Voltages 67 28 DDR II Bias Voltage 67 29 Core Speed and Memory Configuration 68 30 Simulated DDR 333 Topolo...

Page 9: ...Recommendation 108 64 DDR II 400 DIMM Address CMD Lengths 109 65 DDRII 400 Embedded Source Synchronous Routing Recommendations 110 66 DDR II 400 Embedded DQ Lengths 111 67 DDR II 400 Embedded DQS Lengths 112 68 DDRII 400 Embedded Clock Routing Recommendations 113 69 DDR II 400 Embedded Clock PLL Lengths 114 70 DDRII 400 Embedded Address Command Control Routing Recommendations 116 71 DDR II 400 Emb...

Page 10: ...ady mentioned in the previous row Table 51 removed row in Trace Length 80331 signal Ball to Series Termination because the series termination is no longer needed Table 52 Removed Routing Guideline 4 because unbuffered and registered DIMM s have the same topology Deleted Figure 57 because simulations showed that series resistors is no longer needed for DDR 333 DIMM control signals Table 53 Removed ...

Page 11: ...focuses upon specific design considerations for the 80331 and is not intended to be an all inclusive list of all good design practices Use this guide as a starting point and use empirical data to optimize your particular design Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Intel ...

Page 12: ...core and prepreg stacked The finished PCB is heated and cured The via holes are drilled Plating covers holes and outer surfaces Etching removes unwanted copper Board is tinned coated with solder mask and silk screened DDR Double Data Rate Synchronous DRAM Data is clocked on both rising and falling edges of the clock DDR II DDR II is backward compatible with DDR I However it has an increased DDR da...

Page 13: ...MB sec PC2700 JEDEC Names for DDR II based on peak data rates PC2700 clock of 167 MHz 2 data words clock 8 bytes 2672 MB sec PC3200 JEDEC Names for DDR II based on peak data rates PC3200 clock of 200 MHz 2 data words clock 8 bytes 3200 MB sec Downstream At or toward the Primary PCI interface from the Secondary PCI interface Local memory Memory subsystem on the Intel XScale core DDR SDRAM or Periph...

Page 14: ...loper s Manual 273942 Intel Corporation 4 Intel XScale 80200 Processor based on Intel Microarchitecture Developer s Manual 273411 Intel Corporation 5 PCI Local Bus Specification Revision 2 3 PCI Special Interest Group 6 PCI X Specification Revision 1 0b PCI Special Interest Group 7 PCI Bus Power Management Interface Specification Revision 1 1 PCI Special Interest Group 8 IEEE Standard Test Access ...

Page 15: ...ondary bus Address Translation Unit PCI to Internal Bus Application Bridge interfaced to the Secondary Bus High Performance Memory Controller Interrupt Controller with up to 13 external interrupt inputs Two Direct Memory Access DMA Controllers Application Accelerator Messaging Unit Peripheral Bus Interface Unit Performance Monitor Two I2C Bus Interface Units Two 16550 compatible UARTs with flow co...

Page 16: ...ocessor Functional Block Diagram B2472 01 Internal Bus Primary PCI Bus Secondary PCI Bus PCI to PCI Bridge ATU Message Unit 2 Channel DMA Controller Interrupt Controller Timers Application Accelerator Arbiter Intel XScale Core Bus Interface Unit 32 64 bit DDR Interface Memory Controller 16 bit PBI BRG UART Units GPIO 2 1 C Units ...

Page 17: ...unction This diagram is helpful in placing components around the 80331 for the layout of a PCB To simplify routing and minimize the number of cross traces keep this layout in mind when placing components on your board The signals by design are located on the FCBGA package to simplify signal routing and system implementation Table 2 FC style H PBGA Package Dimensions 829 Pin BGA Symbol Minimum Maxi...

Page 18: ... Processor 829 Ball FCBGA Package Diagram B1230 03 E D F1 F2 Die S2 S1 Pin 1 Corner øb e A3 A A1 C Top View Bottom View Side View Seating Plane A 1 2 3 4 B C D E F G H J K L N P R T U V W Y AA AB AC AD AE AF AG AH AJ M 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ...

Page 19: ...M JTAG GPIO PBI VCC VSS Secondary PCI X Bus Primary PCI X Bus AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ...

Page 20: ... JTAG GPIO PBI VCC VSS Primary PCI X Bus Secondary PCI X Bus AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ...

Page 21: ... V core power planes are partitioned on the Intel IQ80331 Evaluation Platform Board IQ80331 Note The voltage for the secondary PCIX bus and primary PCIX bus can be on the same plane Figure 5 Intel 80331 I O Processor Power Plane Layout B2529 01 To Regulators DDR VDD Regulator DDR DIMM Connector Use Top Layer for VTT Plane VCC_DDR VCC 1 5 V VCC_XSCALE ...

Page 22: ...a 80331 Serial ATA adapter card application This entire SATA RAID card adapter can be implemented with just a few chips using the 80331 integrated PCI X bridge and IO processing capability Figure 6 Intel 80331 I O Processor PCI X Adapter Card Block Diagram PCI X Edge Flash Intel 80331 I O Processor DDR II SATA Controller 4 Channel SATA Connectors ...

Page 23: ... page 142 for more information about using with a ICE When not used this signal is be tied to GND This pin has an internal pull up TMS NC when not being used has internal pull up TDI NC when not being used has internal pull up TCK 1 5K pull down when not used GPIO 0 U0_RXD 8 2 K pull up Note GPIO 7 0 initializes as inputs on assertion of P_RST GPIO 1 U0_TXD 8 2 K pull up Note GPIO 7 0 initializes ...

Page 24: ... When PCIODT_EN 0 then 8 2 K pull up is required S_PERR Refer to comments When PCIODT_EN 1 no external pull up needed When PCIODT_EN 0 then 8 2 K pull up is required S_DEVSEL Refer to comments When PCIODT_EN 1 no external pull up needed When PCIODT_EN 0 then 8 2 K pull up is required S_FRAME Refer to comments When PCIODT_EN 1 no external pull up needed When PCIODT_EN 0 then 8 2 K pull up is requir...

Page 25: ...therboard to pull up this signal P_TRDY Refer to comments 8 2 K pull up is required when not already pulled up on the PCI bus An add in card may rely on the motherboard to pull up this signal P_PERR Refer to comments 8 2 K pull up is required when not already pulled up on the PCI bus An add in card may rely on the motherboard to pull up this signal P_DEVSEL Refer to comments 8 2 K pull up is requi...

Page 26: ...2 RETRY 1 5 K pull down when needed refer to comments Configuration Retry Mode RETRY is latched on the rising asserting edge of P_RST and determines when PCI interface of the ATU disables PCI configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the PCI configuration and status register 0 Configuration Cycles enabled Requires pull down resistor 1 Configura...

Page 27: ...n example of this inductor is TDK part number MLZ2012E4R7P 22 µF Capacitor ESR max 0 4Ω ESL 3 0nH Place 22 µF capacitor as close as possible to package pin 0 5 ohm 1 Resistor 1 16W 6 3V 0 5 ohm 1 resistor must be placed between VCC and L The resistor rating is 1 16W Route VCCPLL 1 5 and VSSA 1 5 as differential traces VCCPLL 1 5 and VSSA 1 5 traces must be ground referenced No VCC references Maxim...

Page 28: ... tight tolerance of 40 2 ohm 0 5 DDRRES2 is used as compensation for DDR II OCD Due to the fact that OCD is not supported this pin should be pulled to GND with a 1K resistor Note when not in DDR II mode these pins must have a 1 0 K pull down to GND s Figure 8 Intel 80331 I O Processor DDRRES Resistor Compensation Circuitry DDRRES2 1K ohms DDRRES1 0 1uF 40 2 ohms 0 5 ...

Page 29: ... The recommendations are as follows DDRIMPCRES controls on die termination DDR 385 ohms DDRII 285 ohms Note that the closest standard 1 resistors are acceptable DDRSLWRCRES controls slew rate and driver impedance DDR 845 ohms DDRII 825 ohms With these values the ODT is 150 75 ohms for DDRII and 200 100 ohms for DDR Figure 9 DDR Driver Compensation Circuitry DDRCRES0 DDRSLWCRES 845 ohms DDR DDRIMPC...

Page 30: ...Intel 80331 I O Processor Design Guide Terminations 30 This Page Intentionally Left Blank ...

Page 31: ...er provides guidelines to aid the designer with board layout Several factors influence the signal integrity of a 80331 design These factors include Power distribution Minimizing crosstalk Decoupling Layout considerations when routing the DDR memory DDR II memory and PCI X bus interfaces 4 1 General Routing Guidelines This section details general routing guidelines for designing with 80331 The orde...

Page 32: ...f the distance between the adjacent traces It is also recommended to specify the height of the above reference plane when laying out traces and provide this parameter to the PCB manufacturer By moving traces closer to the nearest reference plane the coupled noise decreases by the square of the distance to the reference plane Avoid slots in the ground plane Slots increases mutual inductance thus in...

Page 33: ...33 Intel 80331 I O Processor Design Guide Routing Guidelines Figure 11 PCB Ground Layout Around Connectors A9260 01 A Incorrect method B Correct method Connector GND PCB Layer Connector Pins ...

Page 34: ...e bulk capacitors can be located anywhere on the board For fast switching currents high frequency low inductance capacitors are most effective Place these capacitors as close to the device being decoupled as possible This minimizes the parasitic resistance and inductance associated with board traces and vias Use an inter plane capacitor between power and ground planes to reduce the effective plane...

Page 35: ...OG dielectric recommended for ceramic capacitors DDR DDRII 2 5 1 8V VCC25 18 1210 22 2 DDR DDRII 2 5 1 8V VCC25 18 7343 150 1 Core 1 5V VCC15 0603 0 1 17 Core 1 5V VCC15 1210 22 2 CPU 1 35V VCC13 0603 0 1 6 CPU 1 35V VCC13 1206 10 1 CPU 1 35V VCC13 1210 22 1 Table 4 Decoupling Recommendations Voltage Plane Voltage Pins Package C µF Number of Caps ...

Page 36: ...trace widths must be adjusted appropriately When wider traces are used the trace spacing must be adjusted accordingly linearly It is highly recommended that a 2D Field Solver be used to design the high speed traces The following Impedance Calculator URL provide approximations for the trace impedance of various topologies They may be used to generate the starting point for a full 2D Field solver ht...

Page 37: ...minates to assure the processor and memory subsystem can be implemented with typical 50 ohm guidelines Dimensions and tolerances for the motherboard are per Table 5 Refer to Figure 12 for location of variables in Table 5 Table 5 Motherboard Stack Up Stripline and Microstrip Sheet 1 of 2 Variable Type Nominal mils Minimum mils Maximum mils Notes Solder Mask Thickness mil N A 0 8 0 6 1 0 The trace h...

Page 38: ... the trace spacing is the result of the tolerances of the trace width Stripline 12 0 Total Thickness mil FR4 62 0 56 0 68 0 Trace Velocity ps in Microstrip 135 141 Velocity varies based on variation in Er It cannot be controlled during the fab process Stripline 167 178 Trace Impedance ohms Microstrip 50 42 5 57 5 Stripline 50 45 55 Table 5 Motherboard Stack Up Stripline and Microstrip Sheet 2 of 2...

Page 39: ... of the tolerances of the trace width Table 6 Adapter Card Stack Up Microstrip and Stripline Variable Type Nominal mils Minimum mils Maximum mils Notes Solder Mask Thickness mil N A 0 8 0 6 1 0 Solder Mask Er N A 3 65 3 65 3 65 Core Thickness mil N A 2 8 3 0 3 2 Core Er N A 4 3 3 75 4 85 2113 material Plane Thickness mil Power 2 7 2 5 2 9 Ground 1 35 1 15 1 55 Trace Height mil 1 3 5 3 3 3 7 The tr...

Page 40: ...1 L2 GND L8 L7 GND Trace Width Total Thickenss Trace Height 1 Plane Thickness Solder Mask Thickness L1 L6 L4 VCC L5 VCC Trace Height 3 L3 Trace Height 2 L3 L6 Microstrip Microstrip Stripline Trace Width Trace Spacing Stripline Core Thickness Microstrip Trace Thickness Stripline Trace Thickness Trace Spacing ...

Page 41: ...guration cycles Configuration cycles allow read and write access to one of the device configuration space registers The IDSEL lines can be mapped to upper address lines which are unused during the configuration cycles The ATU is hardwired to AD30 for IDSEL Note that AD16 typically is reserved for a PCI PCI X bridge Each IDSEL line needs a 200 ohm series resistor on it as shown in the figure below ...

Page 42: ...quest in level one and a low level priority status is assigned to a master request in level two The arbiter checks each of the REQ lines in the first level When none are asserted it traverses to checking level two Once the GNT has been asserted to a master this master has the lowest priority in its level The arbiter also conducts bus parking by driving A D C BE and PAR lines to a known value while...

Page 43: ...signals have no length restrictions P_INT D A S_INT D A and TCK TDI TDO TMS and TRST 6 3 PCI X Topology Layout Guidelines The PCI X Addendum to the PCI Local Bus Specification Revision 1 0a recommends the following guidelines for the number of loads for your PCI X designs Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths Table 7 PCI...

Page 44: ...vershoot in simulation was 1 2 V This fact needs to be taken into consideration when accessing the reliability of your application The following notes should be considered when designing to this section s design guide recommendations 1 The lengths recommended for AD lines are given as a range of length for example 2 0 to 5 0 This means that each AD bit can be routed any where between this range Th...

Page 45: ...istance between clock line and itself a at a minimum of 25 mils apart for serpentine clock layout S_CLKIN gets connected to S_CLKOUT through a 22 ohm resistor The 22 ohm resistor is placed within 1 maximum distance of S_CLKOUT A series termination resistor with the value of 22 ohm resistor is placed within 1 maximum distance of each of the clock outputs SCLKO 3 0 Note Using the value of 33 2 ohm f...

Page 46: ...d be within 25 mills Length Matching Requirements for Topologies having only Slot Each of the Clock out Clk0 Clk3 to the Slots should be length matched to within 25mils The Feedback Clk Feedback Clock is that running from CLKOUT to CLKIN should be routed 3 5 longer than the Clocks running to the Slots This should be done to a tolerance of within 25 mills Length Matching Requirements for Topologies...

Page 47: ...uting Guideline 1 Point to point signal routing needs to be used to keep reflections low Routing Guideline 2 Same number of vias and routing layers as all the other clock lines from the driver to the receiver Table 8 PCI X Clock Layout Requirements Summary Sheet 2 of 2 Parameter Routing Guidelines ...

Page 48: ... Maximum length of breakout region is 500 mils Motherboard Impedance for both microstrip and stripline 50 ohms 15 Add in card Impedance for both microstrip and stripline 57 ohms 15 Stripline Trace Spacing 12 mils from edge to edge Microstrip Trace Spacing 18 mils from edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edge Trace Length 1 TL1 From 80331 signal Ball to firs...

Page 49: ...ils spacing Maximum length of breakout region is 500 mils Motherboard impedance both Microstrip and stripline 50 ohms 15 Add in card impedance both Microstrip and stripline 60 ohms 15 Stripline Trace Spacing 12 mils edge to edge Microstrip Trace Spacing 18 mils edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edge Trace Length 1 TL1 From 80331 signal Ball to first junct...

Page 50: ...round plane Stripline Break out 5 mils on 5 mils spacing Maximum length of breakout region is 500 mils Motherboard impedance both Microstrip and stripline 50 ohms 15 Add in card impedance both Microstrip and stripline 60 ohms 15 Stripline Trace Spacing 12 mils edge to edge Microstrip Trace Spacing 18 mils edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edge Trace Lengt...

Page 51: ...nce both Microstrip and stripline 50 ohms 15 Add in card impedance both Microstrip and stripline 57 ohms 15 Stripline Trace Spacing 12 mils edge to edge Microstrip Trace Spacing 18 mils edge to edge Group Spacing Spacing from other groups 25 mils min center to center Trace Length 1 TL1 From 80331 signal ball to first junction 1 25 minimum 3 0 maximum 1 25 minimum 3 0 maximum Trace Length 3 TL_EM1 ...

Page 52: ...impedance both Microstrip and stripline 50 ohms 15 Add in card impedance both Microstrip and stripline 57 ohms 15 Stripline Trace Spacing 12 mils edge to edge Microstrip Trace Spacing 18 mils edge to edge Group Spacing Spacing from other groups 25 mils min center to center Trace Length TL1 From 80331 signal ball to embedded device 1 25 minimum 2 0 maximum 1 25 minimum 2 0 maximum Trace Length TL2 ...

Page 53: ...trip and stripline 50 Ohms 15 Add in card Impedance microstrip and stripline 57 Ohms 15 Stripline Trace Spacing 12 mils from edge to edge Microstrip Trace Spacing 18 mils from edge to edge Group Spacing Spacing from other groups 25 mils min center to center Trace Length 1 TL1 From 80331 signal Ball to first junction 1 0 minimum 9 5 maximum 1 0 7 0 maximum Trace Length TL2 between junction and conn...

Page 54: ...ripline 50 Ohms 15 Add in card Impedance microstrip and stripline 60 Ohms 15 Stripline Trace Spacing 12 mils from edge to edge Microstrip Trace Spacing 18 mils from edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edger Trace Length 1 TL1 From 80331 signal Ball to first junction 0 5 minimum 3 0 maximum Trace Length TL_EM1 between junction and embedded device 2 5 3 5 max...

Page 55: ...ip and stripline 57 Ohms 15 Stripline Trace Spacing 12 mils from edge to edge Microstrip Trace Spacing 18 mils from edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edge Trace Length 1 TL1 From 80331 signal Ball to first connector CONN1 2 0 minimum 3 75 maximum 2 0 minimum 3 0 maximum Trace Length TL2 first PCI connector CONN1 to second PCI connector CONN2 0 8 minimum 1...

Page 56: ... the breakout is 500 mils Motherboard Trace Impedance microstrip and stripline 50 Ohms 15 Add in card Impedance microstrip and stripline 57 Ohms 15 Stripline Trace Spacing 12 mils from edge to edge Microstrip Trace Spacing 18 mils from edge to edge Group Spacing Spacing from other groups 25 mils minimum edge to edge Trace Length 1 TL1 From 80331signal Ball to first junction 1 5 minimum 4 25 maximu...

Page 57: ...g Topology Table 18 PCI X 66 MHz Slot Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing Maximum length of the breakout is 500 mils Motherboard Trace Impedance microstrip and stripline 50 Ohms 15 Add in card Impedance microstrip and stripline 57 Ohms 15 Stripline Trace Spacing 12 mils fro...

Page 58: ...r length matching for clocks refer clock guidelines Table 8 Number of vias Four vias maximum Table 18 PCI X 66 MHz Slot Routing Recommendations Sheet 2 of 2 Figure 27 PCI X 66 MHz Embedded Routing Topology Table 19 PCI X 66 MHz Embedded Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing M...

Page 59: ...nes Table 8 Number of vias Four vias maximum Table 19 PCI X 66 MHz Embedded Routing Recommendations Sheet 2 of 2 Figure 28 PCI X 66 MHz Mixed Mode Routing Topology Table 20 PCI X 66 MHz Mixed Mode Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for AD Bus Routing Guideline for Upper AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing Maximu...

Page 60: ...um Table 20 PCI X 66 MHz Mixed Mode Routing Recommendations Sheet 2 of 2 Figure 29 PCI 66 MHz Topology Table 21 PCI 66 MHz Slot Table Sheet 1 of 2 Parameter Routing Guideline for AD Bus Routing Guideline for Upper AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing Maximum length of the breakout is 500 mils Motherboard Trace Impedance microstrip and stripli...

Page 61: ...Hz Slot Table Sheet 2 of 2 Parameter Routing Guideline for AD Bus Routing Guideline for Upper AD Bus Figure 30 PCI 66 MHz Embedded Topology Table 22 PCI 66 MHz Embedded Table Sheet 1 of 2 Parameter Routing Guideline for AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing Maximum length of the breakout is 500 mils Motherboard Trace Impedance microstrip and s...

Page 62: ...hing Requirements No length matching is required among datalines For length matching for clocks refer clock guidelines Table 8 Number of vias Four vias maximum Table 22 PCI 66 MHz Embedded Table Sheet 2 of 2 Parameter Routing Guideline for AD Bus Figure 31 PCI 66 MHz Mixed Topology Table 23 PCI 66 MHz Mixed Mode Table Sheet 1 of 2 Parameter Routing Guideline Lower AD Bus Routing Guideline Upper AD...

Page 63: ... datalines For length matching for clocks refer clock guidelines Table 8 Number of Vias Four vias maximum Table 23 PCI 66 MHz Mixed Mode Table Sheet 2 of 2 Parameter Routing Guideline Lower AD Bus Routing Guideline Upper AD Bus Figure 32 PCI 33 MHz Slot Routing Topology Table 24 PCI 33 MHz Slot Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for AD Bus Reference Plane Route over a...

Page 64: ...ength matching for clocks refer clock guidelines Table 8 Number of vias Four vias maximum Table 24 PCI 33 MHz Slot Routing Recommendations Sheet 2 of 2 Figure 33 PCI 33 MHz Embedded Mode Routing Topology Table 25 PCI 33 MHz Embedded Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for Lower AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing...

Page 65: ...s Table 8 Number of vias Four vias maximum Table 25 PCI 33 MHz Embedded Routing Recommendations Sheet 2 of 2 Figure 34 PCI 33 MHz Mixed Mode Routing Topology Table 26 PCI 33 MHz Mixed Mode Routing Recommendations Sheet 1 of 2 Parameter Routing Guideline for lower AD Bus Routing Guideline for upper AD Bus Reference Plane Route over an unbroken ground plane Breakout 5 mils on 5 mils spacing Maximum ...

Page 66: ...5 4 0 maximum Trace Length TL3 to TL5 between connectors 0 75 minimum 1 5 maximum 1 75 minimum 2 75 maximum Length Matching Requirements No length matching is required among datalines For length matching for clocks refer clock guidelines Table 8 Number of vias Four vias maximum Table 26 PCI 33 MHz Mixed Mode Routing Recommendations Sheet 2 of 2 Parameter Routing Guideline for lower AD Bus Routing ...

Page 67: ...ion Unit and Bridge 7 1 DDR Bias Voltages The 80331 supports 2 5 V DDR memory and 1 8V for DDRII Table 27 lists the minimum maximum values for the DDR memory bias voltages and Table 28 lists the minimum maximum values for the DDR II memory bias voltages Table 27 DDR Bias Voltages Symbol Parameter Minimum Maximum Units VCC25 2 5 V Power balls to be connected to a 2 5 V power board plane 2 3 2 7 V V...

Page 68: ...y for both DDR333 and DDR II 400 The DIMM topology supported for the recommendations listed in this section are for x8 single double banks and x16 single double banks DDR333 single DIMM and supports both Buffered Unbuffered DIMM DDRII 400 single DIMM and supports Buffered DIMM Table 29 details the 80331 Core Speed and DDR DDRII memory configuration The DDR interface is divided up into three groups...

Page 69: ...enter was specified Signal Quality analysis covered for Rising flight time Falling flight time Low to high ring back noise margin high High to Low ring back noise margin Low and Low and High Overshoot Crosstalk Analysis was performed for all the major interfaces with actual package models Frequency 167MHz DDR 333 MT s Connector E SPICE of DIMM Connector Derived from SPICE Circuit Package Actual ex...

Page 70: ... a table of recommended topologies for motherboard and add in card eight layer PCB designs Figure 35 provides an example of a cross section used to implement 100 ohm differential trace impedance Throughout this section the important recommendation to meet is the trace impedance The example in Table 31 is provided as a reference ...

Page 71: ...s for DDR Trace Topology Trace Width mils Min Trace Spacing mils Trace Impedance ohms Preferred signals Board Type Microstrip layers 1 or 8 5 5 Breakout Motherboard Add in 7 12 45 Address CMD Control Motherboard Add in 6 12 50 Motherboard Add in 4 12 60 Motherboard Add in 5 note 1 20 100 differential Differential Clock DQS Motherboard Add in Stripline layers 3 or 6 5 5 Break out Motherboard Add in...

Page 72: ...e is an associated strobe DQS for each DQ DM and CB group When data masking is not used system memory DM pins on the DDR needs to be tied to ground The grouping is as follows for the different memory configurations Table 32 x64 DDR Memory Configuration Data Group Associated Strobe DQ 7 0 DM 0 DQS0 DQ 15 8 DM 1 DQS1 DQ 23 16 DM 2 DQS2 DQ 31 24 DM 3 DQS3 DQ 39 32 DM 4 DQS4 DQ 47 40 DM 5 DQS5 DQ 55 4...

Page 73: ...DRAM R Series R Parallel 22 1 5 ohms 51 1 5 ohms Figure 37 Data Group Length Matching B1438 01 Intel 80331 I O Processor DQ Length Y 25 mils Rs Rs Rs Rs Rp VTT Note Datagroup Matching X Y 250 Y mils Datagroup 2 8 DQ Lines Datagroup 1 8 DQ Lines 1 DQS Line DQ Line DQ Length X 25 mils DQ Line DQ Line DQ Line DQ Line Rp VTT Rp VTT Rp VTT DQS Length X mils DQS Length Y mils Rp VTT DQ Line DQ Line DQ L...

Page 74: ... groups 20 mils minimum Series Resistor Rs 22 1 Ω 5 Parallel Termination Single VTT termination of 51 1 Ω 5 to VTT 1 25V or Split terminations of 100 ohms 5 to 2 5V and 100 ohms 5 to ground Place the VTT termination in a VTT island Length Matching Requirements within DQS Group 0 050 within DQS group Length Matching Requirements All DQ DQS lines to Clock The package lengths from Die to Ball provide...

Page 75: ...icrostrip 0 25 0 5 Same as TL2 Fan out for series termination TL4 Vtt Microstrip 0 15 0 5 5 mils Vtt Termination Table 37 Die to Ball Internal Lengths Signal Description Lengths mils BA 0 366 64 BA 1 400 1 CAS 435 86 CB 0 576 97 CB 1 576 96 CB 2 576 99 CB 3 576 99 CB 4 577 86 CB 5 576 95 CB 6 577 CB 7 577 9 CKE 0 768 12 CKE 1 788 7 CS 0 432 83 CS 1 482 04 DDR_VREF 1287 52 DDRCRES0 602 21 DDRIMPCRE...

Page 76: ...16 674 37 DQ 17 675 08 DQ 18 674 24 DQ 19 674 44 DQ 2 801 58 DQ 20 674 16 DQ 21 674 67 DQ 22 674 2 DQ 23 675 04 DQ 24 652 55 DQ 25 652 64 DQ 26 651 67 DQ 27 651 72 DQ 28 652 1 DQ 29 652 61 DQ 3 800 66 DQ 30 652 08 DQ 31 652 58 DQ 32 651 65 DQ 33 650 81 DQ 34 651 69 DQ 35 650 74 DQ 36 650 74 DQ 37 651 71 DQ 38 650 76 DQ 39 650 73 Table 37 Die to Ball Internal Lengths Signal Description Lengths mils...

Page 77: ...3 DQ 5 800 63 DQ 50 805 88 DQ 51 805 96 DQ 52 806 17 DQ 53 806 17 DQ 54 805 54 DQ 55 805 34 DQ 56 767 47 DQ 57 767 45 DQ 58 768 35 DQ 59 767 46 DQ 6 800 62 DQ 60 767 48 DQ 61 767 47 DQ 62 767 63 DQ 63 767 51 DQ 7 800 63 DQ 8 940 16 DQ 9 940 15 DQS 0 801 DQS 1 939 25 DQS 2 674 68 DQS 3 652 66 DQS 4 650 81 DQS 5 701 98 DQS 6 805 94 Table 37 Die to Ball Internal Lengths Signal Description Lengths mil...

Page 78: ...QS 8 577 9 M_CK 0 616 41 M_CK 0 616 27 M_CK 1 762 67 M_CK 1 762 65 M_CK 2 597 08 M_CK 2 597 24 M_RST 760 27 WE 403 92 RAS 290 55 MA 0 326 8 MA 1 447 68 MA 10 352 22 MA 11 390 14 MA 12 620 5 MA 13 485 18 MA 2 338 39 MA 3 483 4 MA 4 505 56 MA 5 629 68 MA 6 634 85 MA 7 403 63 MA 8 638 37 MA 9 393 04 ODT 0 372 29 ODT 1 224 37 Table 37 Die to Ball Internal Lengths Signal Description Lengths mils ...

Page 79: ...79 Intel 80331 I O Processor Design Guide Memory Controller Figure 38 DIMM DQ DQS Topology B 2 5 2 7 V T T 5 1 o h m s 5 D IM M T L 1 T L 2 T L 3 T L 4 2 2 o h m s 5 ...

Page 80: ...acing Notes TL1 Breakout Microstrip Stripline 0 5 5 mils TL2 Lead in Microstrip 2 8 45 ohms 15 or 50 ohms 15 12 mils Lead in traces are preferred as striplines TL3 Microstrip 0 25 0 5 Same as TL2 Fan out for series termination TL4 Vtt Microstrip 0 15 0 5 5 mils Split termination Figure 39 DIMM DQ DQS Split Termination Topology 2 5V 100 ohms 5 DIMM TL1 TL2 TL3 TL4 22 ohms 5 100 ohms 5 GND ...

Page 81: ... drives the command clock in the center of the valid window and the source clocked signals propagate with the command clock signal An important timing specification is the difference between the command clock flight time and the source clocked signal flight time The absolute flight time is not as critical The common clock signal group contains M_CK 2 0 and M_CK 2 0 The following tables and figure ...

Page 82: ...rmination None required 22 1 ohms 5 series termination on each differential segment after the breakout Length matching Requirements The package lengths from Die to Ball provided in Table 37 must be accounted for when length matching Within differential clock pairs 0 025 max within Pairs Intra pair With respect to the DQ DQS group from die to DIMM connector 1 5 max when M_CK is routed Stripline 1 0...

Page 83: ...ption Layer Minimum Length Maximum Length Trace Impedance Spacing Notes TL1 Breakout Microstrip 0 5 5 mils 5 mils trace width OK for breakout TL2 Lead in Microstrip 2 10 Differential Impedance 100 ohms 15 20 mils from others Route as differential pairs Figure 40 DDR 333 Registered DIMM Clock Topology B2526 01 DIMM TL1 TL2 ...

Page 84: ...gurations Table 42 DDR 333 Unbuffered DIMM Clock Topology Lengths Traces Description Layer Minimum Length Maximum Length Trace Impedance Spacing Notes TL1 all 3 clock pairs Breakout Microstrip 0 5 5 mils 5 mils trace width OK for breakout TL2 all 3 x clock pairs Lead in Microstrip Stripline 2 10 Differential Impedance 100 ohms 15 20 mils from others Route as differential pairs Series termination o...

Page 85: ...tion is shown in Table 43 7 4 2 1 1 Control Signal Routing Guidelines Figure 42 and Table 44 provide the routing guidelines for the source clocked group of signals Table 43 Source Clocked Signal Routing DDR SDRAM Rs Series Rp Parallel 51 1 5 ohms Figure 42 Trace Length Requirements for Source Clocked Routing B1457 01 Intel I O Processor DIMM RAS CAS WE 2 9 Rp Rp MA 12 0 BA 1 0 CS 1 0 CKE 1 0 0 15 ...

Page 86: ...20 mils from the Clock DQ DQS groups Series Resistor Rs No series termination required Parallel Resistor Rp 51 1 5 ohms OR Split termination of 100 ohms 5 terminated to 2 5V and 100 ohms 5 terminated to ground Place Vtt terminations in a Vtt island after the DIMM Package Trace Length Breakout Trace Length TL1 Lead in to Connector Trace Length TL2 Parallel Termination Route Length TL3 See Table 37 ...

Page 87: ...87 Intel 80331 I O Processor Design Guide Memory Controller Figure 43 DDR 333 DIMM Unbuffered Registered Address CMD Topology Lengths VTT 1 25 V DIMM TL1 TL2 TL3 51 ohms 5 ...

Page 88: ... Impedance Spacing Notes TL1 Breakout Microstrip or stripline 0 5 5 mils 5 mils trace width OK for breakout TL2 Lead in Microstrip 2 8 5 45ohms 15 50 ohms 15 12 mils from others Within the same group 12 mils Any of the other groups DQ DQS Clock 20 mils TL3 Vtt preferred or Split Termination Microstrip 0 15 0 5 5 mils Single VTT termination in VTT island is preferred ...

Page 89: ... in and Fanout width and spacing 5 mils x 5 mils Microstrip is recommended for pin escapes and terminations Trace Impedance 45 ohm 15 or 50 ohms 15 Trace Spacing trace edge to edge 5 mils is acceptable for pin escapes and fan in fan out from terminations 12 mils between any DQ DQS signals 20 mils bust be maintained from any other groups Package Trace Length The package lengths from Die to Ball pro...

Page 90: ...f 100 ohms 5 to 2 5 V and 100 ohms 5 to ground Routing Guideline 1 Route all data signals and their associated strobes on the same layer Routing Guideline 2 Vias 2 Minimize layer changes especially DQS signals two vias or less Equal number of vias between DQ and its respective DQS signal Table 46 DDR 333 Embedded Source Synchronous Routing Recommendations Sheet 2 of 2 Parameter Routing Guideline ...

Page 91: ...ohms 5 51 ohms 5 SDRAM TL4 TL6 VTT Table 47 Embedded DDR 333 DQ DQS Topology Lengths Traces Description Layer Minimum Length Maximum Length Trace Impedance Spacing Notes TL1 Breakout Microstrip Stripline 0 0 5 5 mils 5 mil trace width breakout OK TL2 Lead in Stripline 1 4 45 ohms 15 or 50 ohms 15 12 mils WIthin the same group 12 mils Any other groups DQ DQS Clock 20 mils TL3 Microstrip 0 0 1 5 mil...

Page 92: ... 333 embedded clock routing guidelines Refer to Table 49 for a description of the segment lengths and matching requirements for buffered clock topology Refer to Table 50 for a description of unbuffered clock topology information Figure 45 Embedded DDR 333 Buffered Clock Topology PLL Feedback SDRAM OUT FB_IN TL0_reg TL0_sdram TL1_sdram TL2_sdram TL2_sdram 120 ohms 5 TL1 T L 2 TL0 TL0_PLLFB TL3_PLLF...

Page 93: ...en length matching See respective registered Table 49 and unbuffered Table 50 tables Topology Trace Length tables for additional information Within Differential Clock pairs 0 025 max within Pairs Intra pair Registered Clock from IOP Die to PLL Input with Respect to DQS With in 1 0 of all strobes DQS0 8 strobe length measured from IOP die to SDRAM Registered Clock from IOP Die to PLL Input with Res...

Page 94: ... Stripline 0 5 5 mils Differential Routing TL1 Lead in Microstrip Stripline 2 8 Differential Impedance of 100 ohms 15 20 mils from others TL2 Termination 0 2 5 mils TL0_PLL FB 2 3 Same as TL1 20 mils from others Route per DDR1 JEDEC TL2_PLL FB Termination 0 3 Route per DDR1 JEDEC TL3_PLL FB 0 05 0 09 Same as TL1 Route per DDR1 JEDEC TL0_sdra m 2 5 Same as TL1 Route per DDR1 JEDEC TL1_sdra m Termin...

Page 95: ...ls from any other signals Match within 1 of strobes DQS from controller to SDRAM and within 1 of Address CMD control from controller to SDRAM input Route as T Differential pairs as per DDR1 DIMM JEDEC TL1 0 47 0 49 Same as TL0 20 mils Route per DDR1 JEDEC TL2 0 72 0 73 Same as TL0 20 mils Route per DDR1 JEDEC TL3 0 36 0 37 Same as TL0 20 mils Route per DDR1 JEDEC TL4 Breakout Any 0 5 5 mils Route ...

Page 96: ...ered memory implementations i e single bank w less than or equal to 36pF input capacitance Microstrip Trace Width and spacing 5 mils x 5 mils Microstrip is recommended for pin escapes and terminations Trace Impedance 45 ohm 15 or 50 ohms 15 Trace Spacing trace edge to edge 5 mils is acceptable for pin escapes and terminations 12 mils within group 20 mils must be maintained from any other groups Cl...

Page 97: ...than or equal to 36pF all ADD CMD CTRL trace lengths must be 1 0 to 2 0 shorter than M_CK s trace length Number of vias For Un buffered memory implementations Maximum of 5 For Registered memory implementations Maximum of 5 from IOP die to register Maximum of 6 from Register to SDRAM Routing Guideline 1 Topology shown is based on a Raw B implementation Refer to JEDEC Un buffered DIMM specs for Raw ...

Page 98: ...0 5 0 6 Same as TL1 12 mils Fan out for series termination only for unbuffered TL4 0 3 0 35 Same as TL1 12 mils TL5 0 14 0 18 Same as TL1 12 mils TL6 0 32 0 35 Same as TL1 12 mils TL7 0 25 0 5 Same as TL1 12 mils TL8 Breakout Any 0 0 5 5 mils TL9 Lead in Microstrip Stripline 1 8 45 ohms 15 or 50 ohms 15 12 mils Spacing within the same group 12 mils With other groups 20 mils TL10 VTT Microstrip 0 2...

Page 99: ... mils trace width for breakout TL2 Microstrip 0 6 1 37 45 ohms 15 or 50 ohms 15 12 mils Spacing within the same group 12 mils Other groups 20 mils TL3 1 39 2 57 Same as TL2 12 mils TL4 0 4 0 56 Same as TL2 12 mils TL5 0 14 0 15 Same as TL2 12 mils TL6 0 48 0 63 Same as TL2 12 mils TL7 0 20 0 32 Same as TL2 12 mils TL8 0 49 0 72 Same as TL2 12 mils TL9 Lead in Microstrip 1 9 45 ohms 15 or 50 ohms 1...

Page 100: ...Figure 48 Embedded DDR 333 Registered ADDR CMD Topology TL6 TL5 TL4 TL6 TL6 TL4 TL5 TL6 Register TL7 TL7 TL7 TL7 TL7 TL7 TL7 TL7 TL3 TL3 TL2 SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin TL8 SDRAMPin VTT 1 25V 51ohms 5 TL1 TL9 TL10 TL11 ...

Page 101: ...ust be programmed for both the IOP and the SDRAM locations The Table 54 and Table 55 list the DDR II differential strobe alignment with each of the DQ groups Table 54 x64 DDR Memory Configuration Data Group Positive Strobe Negative Strobe DQ 7 0 DM 0 DQS0 DQS0 DQ 15 8 DM 1 DQS1 DQS1 DQ 23 16 DM 2 DQS2 DQS2 DQ 31 24 DM 3 DQS3 DQS3 DQ 39 32 DM 4 DQS4 DQS4 DQ 47 40 DM 5 DQS5 DQS5 DQ 55 48 DM 6 DQS6 D...

Page 102: ...acing recommendations are for trace edge to edge except for differential pairs in which center to center was specified Timing analysis was conducted ISI Pattern was simulated for all the major topologies Signal Quality analysis covered for Rising flight time Falling flight time Low to high ring back noise margin high High to Low ring back noise margin Low and Low and High Overshoot Crosstalk Analy...

Page 103: ...enter distance of 12 mils refer to Figure 35 3 Strip Differential Lines Add in stripline 100 ohms Constructed by two striplines of 4 mils traces separated by center to center distance of 13 mils refer to Figure 35 Table 57 Example Topology for DDRII Trace Width Impedance Requirements Topology Trace Width mils Min Trace Spacing mils Trace Impedance ohms Preferred signals Board Type Microstrip layer...

Page 104: ...DR II 400 DIMM Source Synchronous Routing This section lists the recommendations for the DDR II 400 Source Synchronous Routing These signals include all the DQ DQS DM signals Refer to Figure 49 and Table 58 for a block diagram of the lengths and matching requirements Figure 49 Intel 80331 I O Processor DDRII 400 DIMM Source Synchronous Routing DQ Group 2 D I M M 2 0 8 0 I O Processor DQS Group 2 8...

Page 105: ...Signals Differential ended strip lines at 100ohm impedance Refer to Table 57 and DIMM DQS Topologies DQ Group Spacing edge to edge Spacing same group 12 mils minimum Spacing from other DQ groups 20 mils minimum For DQS from any other signals 20 mils minimum Overall Trace Length 80331 signal Ball to DIMM connector no series connector 2 minimum to 8 maximum correlated with the clock length from ball...

Page 106: ...IMM DQS Lengths Traces Description Layer Minimum Length Maximum Length Trace Impedance Spacing edge to edge Notes TL0 Breakout Microstrip 0 0 5 5 mils 5 mils trace width OK for breakout TL1 Lead in Microstrip 2 8 Differential 100 ohm impedance 20 mils from other signals Route as differential pair Motherboard 100 ohm differential constructed by stripline of two 4 mil traces separated by center to c...

Page 107: ...nector Length Matching Within differential clock signals With respect to DQ DQS group from controller to DIMM connector With respect to address command group from controller to DIMM connector 0 0250 within pairs intra pair 1 0 maximum 1 0 maximum Routing Guideline 1 Maximum of 1 via layer change for differential clocks use the same number of vias between and signals of differential clock Routing G...

Page 108: ...reakout regions 12 mils within group 20 mils from any other clock DQ DQS groups Trace Impedance 45 ohms 15 or 50 ohms 15 Trace Length Overall length from 80331 signal Ball to DIMM Connector 2 0 min to 10 max Correlated with in 1 of DQ DQS and command lead in MB length Refer to following table for segment lengths Length Matching Requirements 2 10 matched within 1 of target motherboard M_CK Single P...

Page 109: ... OK for breakout TL1 Lead in Microstrip 2 10 45 ohms or 50 ohms 12 mils 45 ohm 15 or 50 ohm 15 2 10 matched within 1 of target motherboard M_CK TL2 Vtt Microstrip 0 15 0 5 5 mils Place terminations in Vtt island Figure 53 DDR II 400 DIMM Address CMD Topology Figure 54 DDR II 400 DIMM Address CMD Split Termination Topology TL0 TL1 DIMM V TT 0 9 V Rp 51 ohms 5 TL2 T L 0 T L 1 D IM M 1 8 V R p 1 0 0 ...

Page 110: ...ms 15 Differential impedance of 100 ohms 15 Trace Details TL1 and TL4 are approximately same length and the series Termination to be placed in the middle of lead in trace for Lead in lengths 6 Inches When Controller to SDRAM lead in trace length is less than 6 Inches Series Termination may be placed anywhere between middle of the lead in trace to SDRAM For DQS use differential routing Route all da...

Page 111: ... 400 Embedded DQ Lengths Traces Description Layer Minimum Length Maximum Length Trace Impedance Spacing Notes TL0 Breakout Microstrip 0 0 5 5 mils 5 mils trace width OK for breakout TL1 Lead in Stripline 1 4 45 ohms or 50 ohms 12 mils 45 ohms 15 50 ohms 15 TL2 Microstrip 0 0 1 5 mils 5 mils trace width OK for termination fan out TL3 Microstrip 0 0 1 5 mils 5 mils trace width OK for termination fan...

Page 112: ... 400 Embedded DQS Lengths Traces Description Layer Minimum Length Maximum Length Trace Impedance Spacing Notes TL0 Breakout Microstrip 0 0 5 5 mils 5 mils trace width OK for breakout TL1 Lead in Stripline 1 4 Differential impedance of 100 ohms 15 20 mils from others TL2 Microstrip 0 0 1 5 mils trace width OK for termination fan out TL3 Microstrip 0 0 1 Same as TL2 TL4 Same as TL1 Stripline 1 in 4 ...

Page 113: ...ace Impedance Differential impedance of 100 ohms 15 Refer to Figure 57 Trace Details Route as differential pair with differential impedance of 100 ohms Figure 57 Overall Trace Length 2 0 min to 10 0 max refer to figures and tables that follow for line segment lengths and topology DQS Length Matching Within differential clock signals 0 0250 within pairs intra pair Overall clock correlation with oth...

Page 114: ... 2 3 Same as TL1 20 mils Route as per DDRII JEDEC TL1_PLLFB Microstrip or stripline 20 mils 50 mils 20 mils Route as per DDRII JEDEC TL2_PLLFB For Termination Microstrip or stripline 0 100 mils 5 mils Route as per DDRII JEDEC TL0_sdram Microstrip Str ipline 2 7 2 75 Same as TL1 20 mils from others Route as per DDRII JEDEC TL1_sdram Microstrip Str ipline 0 5 0 75 20 mils from others Route as per DD...

Page 115: ...lock Topology Feedback SDRAM FB_IN Intel I O Processor PLL SDRAM Rp 120 ohms 5 OUT Rp 120 ohms 5 TL0_reg TL0_sdram TL1_sdram TL2_sdram TL2_sdram Rp 120 ohms 5 TL1 T L 2 TL0 TL0_PLLFB TL1_PLLFB TL2_PLLFB Register Rp 240 ohms 5 Register Rp 240 ohms 5 TL1_reg TL1_reg TL2_reg TL2_reg ECC Optional ...

Page 116: ...ogy Microstrip Trace Spacing edge to edge 5 mils acceptable through pin field break out regions and terminations 12 mils within group 20 mils from any other clock DQ DQS groups Overall length 80331 signal Ball to register input 2 minimum 10 maximum length matched within 1 0 of target motherboard clock M_CK to PLL Series Termination none Parallel Termination 51 ohms place the VTT terminations in th...

Page 117: ...mils 45 ohms 15 or 50 ohms 15 TL2 Microstrip MS 20 mils 25 mils Same as TL1 12 mils TL2 to TL8 as per JEDEC DDRII Registered specification routed as T points TL3 MS 1500 mils 1550 mils Same as TL1 12 mils TL4 MS 1850 1900 Same as TL1 12 mils TL5 MS 500 560 Same as TL1 12 mils TL6 MS 275 325 Same as TL1 12 mils TL7 MS 550 600 Same as TL1 12 mils TL8 MS 50 270 Same as TL1 12 mils TL9 Fan out MS 0 10...

Page 118: ...8 DDR II 400 Embedded Address Control Topology TL7 TL6 TL6 TL7 TL5 TL5 TL5 TL5 Register TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL4 TL3 TL2 SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin Intel I OProcessor TL0 TL1 TL9 VTT 0 9V 51 ohms 5 TL10 ...

Page 119: ... 400 Embedded Address Control Topology With Split Termination TL7 TL6 TL6 TL7 TL5 TL5 TL5 TL5 Register TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL8 TL4 TL3 TL2 SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin SDRAMPin TL0 TL1 TL9 1 8V 100 ohms 5 TL10 100 ohms 5 GND ...

Page 120: ...ation resistor per signal Decouple the VTT plane using one 0 1 µF decoupling capacitor per two termination resistors Each decoupling capacitor must have at least two vias between the top layer ground fill and the internal ground plane In addition place one 10 µF or larger 100 µF suggested Tantalum capacitor on each end of the termination island for bulk decoupling Figure 60 provides an example of ...

Page 121: ...e maximum current of 2 6 A 2 9 A for a 64 72 bit DIMM 7 8 DDR VREF Voltage The Figure 61 shows the DDR Vref voltage The DDR VREF is a low current source supplying input leakage and small transients It must track 50 percent of VDDQ VSSQ over voltage temperature and noise Use a single source for VREF to eliminate variation and tracking of multiple generators Maintain 15 20 mils clearance around othe...

Page 122: ...122 Intel 80331 I O Processor Design Guide Memory Controller ...

Page 123: ...for Flash Memory devices 8 1 Peripheral Bus Signals Bus signals consist of two groups address data and control status 8 1 1 Address Data Signal Definitions The address data signal group consists of 26 lines 16 of these signals multiplex within the processor to serve a dual purpose During and address cycle TA the processor drives A 22 16 and AD 15 0 with the address of the bus access At all other t...

Page 124: ...ovide the demultiplexed byte address for a read burst 16 bit region A 2 1 provide the demultiplexed short word address for a read burst Note When using a 16 bit flash device mode A0 is a don t care During initialization bus width is selected for each of the two address ranges in the Peripheral Base Address Registers PBBAR0 PBBAR1 In addition the PBBAR0 PBBAR5 can be used to configure these ranges ...

Page 125: ...fault bank 0 is enabled with the maximum number of Address to Data and Recovery Wait states The width of the interface can be strapped for either 8 bit wide Flash or 16 bit wide flash Thus PCE0 is the Peripheral Bus chip enable to be used for booting purposes Figure 63 shows how two 8 bit Flash devices interface with 80331through the PBI Interface z Refer to Table 72 for the programmable address t...

Page 126: ... bit address data bus interfacing with one or two asynchronous flash devices operating at 66MHz 50 ohm mother board and 60 ohm add in card stackups were considered Lossy uncoupled transmission lines were used for the simulations Trace spacing were set 3X height of trace over reference plane to avoid crosstalk The width of the bus 8 16 bits and the number of flash devices yields six discrete topolo...

Page 127: ...d plane or power plane If routing over power plane maintain this consistency throughout the topology Breakout 5 mils on 5 mils spacing Maximum length of breakout region is 500mils Routing Microstrip or stripline or combination of microstip and stripline Motherboard Impedance for both microstrip and stripline 50 ohms 15 Add in card Impedance for both microstrip and stripline 60 ohms 15 Trace Spacin...

Page 128: ...ripline or combination of microstip and stripline Motherboard Impedance for both microstrip and stripline 50 ohms 15 Add in card Impedance for both microstrip and stripline 60 ohms 15 Trace Spacing center to center 12 mils between all AD lines 20 mils must be maintained from all other signals or vias Trace Length TL1 2 0 to 10 0 Trace Length to TL2 0 5 to 2 0 Trace Length to strapping resistors 0 ...

Page 129: ... microstrip and stripline 50 ohms 15 Add in card Impedance for both microstrip and stripline 60 ohms 15 Trace Spacing center to center 16 mils for microstrip 60 ohms or stripline 50 60 ohms to 20 mils for microstrip 50 ohms Trace Spacing center to center 12 mils between all AD lines 20 mils must be maintained from all other signals or vias Trace Length TL1 2 0 to 10 0 Trace Length TL2 TL3 0 5 to 2...

Page 130: ...Intel 80331 I O Processor Design Guide Peripheral Local Bus 130 This Page Intentionally Left Blank ...

Page 131: ...erations including during system power up and power down In other words the following must always be true VCC33 VCC15 0 5V This can be accomplished by placing a diode with a voltage drop 0 5V between VCC15 and VCC33 an Anode is connected to VCC15 and a cathode is connected to VCC33 If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is powered the maximum allowable tim...

Page 132: ...less of the state of Vcc powering the 80331 9 2 2 Power Failure Sequence Upon initial power up a power supply provides appropriate voltage to the system The voltage level increases at a rate dependent on the type of power supply used and components in the system In the specification Tfail is defined as the time when P_RST is asserted in response to the power rail going out of specification Tfail i...

Page 133: ... the 10 K and the combined value 12 1 K and 3 01 K 1 resistors This ratio provides a trip point value of 2 96 V When the 3 3 V rail falls below the 2 96 V level the PWGD signal is forced low In the CRB the P_RST secondary side reset is tied to the P_RST pin of the IOP The P_RST triggers the power fail sequence 9 2 3 Power Delay The 80331provides a dedicated input pin PWRDELAY that will be used to ...

Page 134: ...y in Figure 68 is battery powered It allows maintaining the CKE 1 0 signals low while the system power is off The latches are cleared when the 80331 drives CKE 1 0 low with a self refresh command and are reset when PWRGD is driven from low to high after system power is recovered During normal operation the CKE signals are controlled by the 80331 When the power is turned off the battery powered lat...

Page 135: ...ese steps Pull DDR CKE pins high and leave CKE signals on 80331 as no connects This keeps SDRAM from entering a pseudo self refresh mode which can cause a lock up condition on the SDRAM device Pull the PWRDELAY pin low through a 1 5 K pull down Pulling it low has the effect of keeping the power fail state machine in reset therefore not allowing the power fail sequence to ever occur ...

Page 136: ...Intel 80331 I O Processor Design Guide Power Delivery 136 This Page Intentionally Left Blank ...

Page 137: ...es an overview of the IQ80331 features and describes the circuits specific to the IQ80331 k j Figure 69 Intel IQ80331 Evaluation Platform Board CRB Block Diagram B2531 01 Intel 80331 I O Processor Buzzer 8 MB Intel StrataFLASH Technology Local Bus C FLASH Gig E Secondary PCI X Bus 100 MHz DDR SDRAM Battery Backup HEX LED RS 232 Slot Primary PCI X Bus 133 MHz Edge Connector DDR ii 400 RS 232 I2C GP...

Page 138: ...J11 serial port connectors on the bracket Compact Flash Connector JTAG connector for the CPU and CPLD Header Ιinterrupt GPIO header Peripheral bus debug expansion header 20 pin JTAG header for CPU and CPLD access 3 pin header for each I2 C bus Logic Analyzer Probing Provide access through standard connectors i e PCI X Misc Functions Temperature sensor Compact Flash Audible Alarm Buzzer Power On LE...

Page 139: ...alleviate potential problems 11 1 Requirements The Intel 80331 I O processor 80331 like many others requires that nTRST Tap Reset is asserted during power up This is to ensure a fully initialized boundary scan chain Failure to comply with this requirement may result in spurious behavior of the application The ARM Multi ICE JTAG debugger requires that nTRST is always weakly pulled high This require...

Page 140: ...ain difference to be noted is the specific implementation of nTRST for each debugger The Macraigor Raven implementation actively drives nTRST high and low The WindRiver Systems visionPROBE visionICE can configure nTRST active or open collector only drive low ARM Multi ICE is configured as open collector only Figure 71 JTAG Header Pin Out A8982 01 1 3 5 7 9 11 13 15 17 19 VTref nTRST TDI TMS TCK RT...

Page 141: ...lows the debugger to get the TAP controller in a known state The nSRST signal allows the debugger to control system processor reset in order to download the debug handler via the JTAG interface Figure 72 and Figure 73 are used as examples without reflecting actual signal timings Figure 72 JTAG Signals at Powerup Figure 73 JTAG Signals at Debug Startup A9279 01 nSRST TD0 TCK TMS TDI nTRST VCC A9280...

Page 142: ...en configured as active do not require any special power up circuitry The requirement is that nTRST is weakly pulled down at the processor It is suggested that the value of the pull down resistor is 10 KΩ or greater The value of this resistor needs to be confirmed with the JTAG debugger manufacturer to ensure optimal performance 11 4 2 ARM Multi ICE The ARM Multi ICE debugger requires special powe...

Page 143: ...ch allow ease of viewing the PCI signals on an Agilent Technologies Logic Analyzer Refer to the following test equipment that is used for this analysis Two AMP 2 767004 2 surface mount connectors mounted on the target board and routed to the PCI X Local bus Two Agilent E5346A or E5351A High Density Adapter Cables from FuturePlus System or Agilent Technologies Four logic analyzer PODS FS1104 Softwa...

Page 144: ...1 13 C BE2 13 12 C BE3 15 11 IDSEL 17 10 REQ 19 9 GNT 21 8 INTD 23 7 INTC 25 6 INTB 27 5 INTA 29 4 UNUSED 31 3 UNUSED 33 2 UNUSED 35 1 UNUSED 37 0 UNUSED Table 80 Logic Analyzer Pod 3 Mictor 38 2 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 6 CLK 16 IRDY 8 15 AD15 10 14 AD14 12 13 AD13 14 12 AD12 16 11 AD11 18 10 AD10 20 9 AD09 22 8 AD08 24 7 AD07 26 6 AD06 28 5 AD05 30 4 AD0...

Page 145: ...30 11 13 AD29 13 12 AD28 15 11 AD27 17 10 AD26 19 9 AD25 21 8 AD24 23 7 AD23 25 6 AD22 27 5 AD21 29 4 AD20 31 3 AD19 33 2 AD18 35 1 AD17 37 0 AD16 Table 82 Logic Analyzer Pod 5 Mictor 38 3 Pin Number Odd Pod Logic Analyzer Channel Number PCI X Signal Name 6 CLK 16 PAR64 8 15 AD47 10 14 AD46 12 13 AD45 14 12 AD44 16 11 AD43 18 10 AD42 20 9 AD41 22 8 AD40 24 7 AD39 26 6 AD38 28 5 AD37 30 4 AD36 32 3...

Page 146: ...lace the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the mictor connectors The connection from the mictors to the logic analyzer must then be done with the E5351A The E5346A contains the logic analyzer termination circuitry the E5351A does not Table 83 Logic Analyzer Pod 6 Mictor 38 Pin Number Even Pod Logic Analyzer...

Page 147: ...book Brian C Wadell Microstrip Lines and Slotlines K C Gupta Et al PCI X Addendum to the PCI Local Bus Specification Revision 1 0a PCI X Electrical Subgroup Report Version1 0 Design Modeling and Simulation Methodology for High Frequency PCI X Subsystems Moises Cases Nam Pham Dan Neal www pcisig com PCI Local Bus Specification Revision 2 3 PCI Special Interest Group 1 800 433 5177 High Speed Digita...

Page 148: ...el 80331 I O Processor Design Guide References 13 2 Electronic Information b Table 86 Electronic Information The Intel World Wide Web WWW Location http www intel com Customer Support US and Canada 800 628 8686 ...

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