Intel 6300ESB ICH, Design Manual

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January 2007 85
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.3.2.2 ITP Interposer Design Guidelines for Production Systems
For production systems that do not use the ITP interposer, observe the following guidelines to
ensure that all necessary signals are terminated properly.
Table 7 summarizes all the signals that require termination when a system does not use the ITP
interposer. This includes TDI, TMS, TRST#, and TCK. TDO may be left as a no connect.
The series 33
Ω
and 49.9
Ω
± 1 percent parallel termination resistors on the ITP_CLK/ITP_CLK#
differential host clock inputs to the processor socket may also be depopulated for production
systems. The only requirement is that the BIOS should disable the third differential host clock pair
routed from the CK409 clock chip to the Intel Pentium M/Celeron M processor socket.
Finally, the 150
Ω
to 240
Ω
pull-up resistor for the DBR# output signal from processor socket may
or may not be depopulated depending on how it affects the system reset logic that it is connected to.
Thus, it is the responsibility of the system designer to determine whether termination for DBR# is
required or not for a given system implementation. The same is also true for DBA# if implemented.
This signal is not required and may be left as no connect. However, it is the responsibility of the
system designer to determine whether termination for DBA# is required.
4.3.3 Logic Analyzer Interface (LAI)
Intel is working with Agilent Corporation to provide logic analyzer interfaces (LAIs) for use in
debugging Intel Pentium M/Celeron M processor-based systems. LAI vendors should be contacted
to get specific information about their logic analyzer interfaces. The following information is
general; specific information must be obtained from the logic analyzer vendor.
Due to the complexity of a Intel Pentium M/Celeron M processor-based system, the LAI is critical
in providing the ability to probe and capture Intel Pentium M/Celeron M processor system bus
signals. There are two sets of considerations to keep in mind when designing a Intel Pentium
M/Celeron M processor-based system that may make use of a LAI: mechanical and electrical.
Figure 39. ITP_CLK to CPU ITP Interposer Layout Example
PRIMARY SIDE
SECONDARY
SIDE
ITP_CLK
ITP_CLK#
A16, A15 pins
CK - 408
33 ?
49.9 ?
PRIMARY SIDE
LAYER 6
SECONDARY
SIDE
ITP_CLK
ITP_CLK#
A16, A15 pins
CK409
33
Ω
49.9
Ω