January 2007
81
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.3.1.2
ITP Signal Routing Example
illustrates a recommended layout example for the ITP700FLEX signals. The
ITP700FLEX connector is placed on the primary side of the motherboard and results in a smooth,
straight-forward routing solution.
Note:
The V
CCP
(1.05 V) power delivery continues from the Intel Pentium M/Celeron M processor
socket cavity on the secondary side of the motherboard through the pin field as shown on the right
side of
. Three V
CCP
vias in conjunction with three ground stitching vias allow a
transition to the primary side to connect to the VTT and VTAP pins of the ITP700FLEX connector
and a transition back to the secondary side of the motherboard. A small V
CCP
flood is created on
the secondary side under the body of the ITP700FLEX connector with a 0.1 µF decoupling
capacitor. This provides a convenient connection for the 220
Ω
and 54.9
Ω
pull-ups for RESET#
and TDO signals as well as the 39.2
Ω
pull-up for the TMS signal.
Notice the very short trace from the 22.6
Ω
series resistors for the RESET# and TDO signals to the
ITP700FLEX pins. Refer to
for more details on RESET# signal routing.
The 150
Ω
TDI pull-up is connected to the V
CCP
(1.05 V) flood on the secondary side close to Intel
Pentium M/Celeron M processor pin.
The ITP700FLEX TCK pin has a 27.4
Ω
pull-down to ground very close to the ITP700FLEX
connector and routes to the Intel Pentium M/Celeron M processor’s TCK pin and loops back with
no stub to the FBO pin of the ITP700FLEX connector.
BCLKp/BCLKn are routed in this example on Layer 3. For more BCLKp/BCLKn routing details,
refer to
.
All other signals incorporate a straight forward routing methodology between the ITP700FLEX
and Intel Pentium M/Celeron M processor pins.
VTAP
Short to VCCP plane
VCCP (1.05 V)
VTT
Short to VCCP plane
VCCP (1.05 V)
Add 0.1 µF decap within 0.1 inch
of VTT pins of ITP700FLEX
connector
NOTES:
1. Refer to
2. Refer to
for more information.
3. All the needed terminations to ensure proper signal quality are integrated inside the Intel Pentium
M/Celeron M processor AGTL+ buffers or inside the ITP700FLEX debug port. No need for any external
components for the BPM[5:0]# signals.
4. Only required if DBA# is used with any target system circuitry. This signal may be left unconnected if
unused.
5. In cases where a system is designed to use the ITP700FLEX debug port for debug purposes but the
ITP700FLEX connector may or may not be populated at all times although the signal routing and
termination or decoupling components are implemented, the component placement guidelines should
adhere to the ones listed. However, for signals where the termination component placement guidelines for
non-ITP700FLEX supported systems (see
) are more restrictive or conservative than the
component placement guidelines for the ITP700FLEX supported case, then the more
conservative/restrictive guidelines should be followed.
Table 19. Recommended ITP700FLEX Signal Terminations (Sheet 2 of 2)
Signal
Termination Value
Termination Voltage
Termination/Decap Location
Notes
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
