Intel 6300ESB ICH, Design Manual

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316
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
13.3.6 PCI-X Layout Checklist
13.3.7 PCI Layout Checklist
13.3.8 FWH Decoupling Layout Checklist
5 RTC signals should be ground referenced.
Table 156. PCI-X Layout Checklist
# Layout Recommendations Comments
1
Eight inches maximum to the first slot, then 1.5 inches to each
subsequent slot.
PCI-X clocks and loop-back clocks are scaled accordingly. (See
Section 9.10.1 through Section 9.10.2 for more information.)
2
Place the PXRCOMP pull-down resistor as close to the 6300ESB
as possible
3 IDSEL (See Section 9.10.2 .)
4
Signals should be routed with 5 mils trace width and 12 mils
spacing. (edge-to-edge)
Table 157. PCI Layout Checklist
# Layout Recommendations Comments
1
Ten inches maximum to the first slot, then one inch to each
subsequent slot.
PCI clocks and loop-back clocks are scaled accordingly (see
Figure 120 for more information).
2
Signals should be routed with 5 mils trace width and 7 mils
spacing.(edge-to-edge)
3
Clock signals should be routed with 5 mils trace width and 50 mils
spacing.(edge-to-edge)
4 IDSEL (See Section 9.10.2 for more information.)
Table 158. FWH Decoupling Layout Checklist
# Layout Recommendations Comments
1
0.1 µF capacitors should be placed between the V
CC
supply pins
and the V
SS
ground pins, no less than 390 mils from the V
CC
supply pins.
2
4.7 µF capacitors should be placed between the V
CC
supply pins
and the V
SS
ground pins, no less than 390 mils from the V
CC
supply pins.
Table 155. RTC Layout Checklist
# Layout Recommendations Comments