Intel 6300ESB ICH, Design Manual

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January 2007 27
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Overview
2.3 Component Features
2.3.1 Intel
®
Pentium
®
M Processor
2.3.1.1 Architectural Features
•
On-die primary 32 Kbyte instruction cache and 32 Kbyte write-back data cache
•
On-die 1 Mbyte second level cache
•
Supports Streaming SIMD Extensions 2 (SSE2)
•
Assisted Gunning Transceiver Logic (AGTL+) bus driver technology
•
Enhanced Intel SpeedStep
®
technology to enable real-time dynamic switching between
multiple voltage and frequency points
•
Supports host bus Dynamic Bus Inversion (DINV)
•
Dynamic power down of data bus buffers
•
BPRI# control to disable address/control buffers
2.3.1.2 Packaging/Power
•
478-pin, Micro-FCPGA and 479-ball Micro-FCBGA packages
•
VCC-CORE for Intel
®
Pentium
®
M Processor at 1.6GHz: 1.484 V (highest frequency mode)
to 0.956 V (lowest frequency mode); VCCA (1.8 V); VCCP (1.05 V)
•
VCC-CORE for Low Voltage Intel
®
Pentium
®
M Processor at 1.1 GHz: 1.180 V (highest
frequency mode) to 0.956 V (lowest frequency mode); VCCA (1.8 V); VCCP (1.05 V)
•
TDP: 24.5 W for the Intel
®
Pentium
®
M Processor at 1.6 GHz
•
TDP: 12 W for the Low Voltage Intel
®
Pentium
®
M Processor at 1.1 GHz
2.3.2 Intel
®
Pentium
®
M Processor on 90 nm Process with 2 MB
L2 Cache
All features of the Intel Pentium M processor are supported by the Intel Pentium M Processor on
the 90 nm process with 2 MB L2 cache. The processors also utilize the same package and footprint.
This section only lists the additional on-die enhancements. For more details, see the Intel Pentium
M Processor on 90nm Process with 2 MB L2 Cache Datasheet.
New features on the Intel Pentium M Processor on the 90nm process with 2MB L2 cache include:
•
On-die 2-MB L2 cache
•
Strained silicon process technology
Voltage and Power Changes:
•
Intel
®
Pentium
®
M Processor 745 (90 nm, 2 MB L2 Cache, 1.8 GHz, 400 MHz FSB):
— V
CC-CORE (HFM)
: 1.276 V – 1.340 V
— V
CC-CORE (LFM)
: 0.988 V
— V
CCA
: 1.8 V only
— TDP: 21 W