Intel 6300ESB ICH, Design Manual

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240
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.13 FWH
9.13.1 FWH Vendors
The following vendors manufacture firmware hubs that conform to the Intel
®
FWH Specification .
Contact the vendor directly for information on packaging and density.
SST http://www.sst.com/
STM http://www.st.coml
ATMEL http://www.atmel.com
9.13.2 FWH Decoupling
A 0.1
µ
F capacitor should be placed between the V
CC
supply pins and the V
SS
ground pins to
decouple high frequency noise, which may affect the programmability of the device. Additionally,
a 4.7
µ
F capacitor should be placed between the V
CC
supply pins and the V
SS
ground pins to
decouple low frequency noise. The capacitors should be placed no further than 390 mils from the
V
CC
supply pins.
9.13.3 In-circuit FWH Programming
All cycles destined for the FWH appear on PCI. The 6300ESB Hub Interface to PCI Bridge places
all CPU boot cycles out on PCI (before sending them out on the FWH interface). When the
6300ESB is set for subtractive decode, these boot cycles may be accepted by a positive decode
agent on the PCI bus. This enables the ability to boot from a PCI card that positively decodes these
memory cycles. In order to boot from a PCI card, it is necessary to keep the 6300ESB in
subtractive decode mode. When a PCI boot card is inserted and the 6300ESB is programmed for
positive decode, there are two devices positively decoding the same cycle.
9.13.4 FWH INIT# Voltage Compatibility
The FWH INIT# signal trip points need to be considered because they are NOT consistent among
different FWH manufacturers. The INIT# signal is active low. Therefore, the inactive state of the
6300ESB INIT# signal needs to be at a value slightly higher than the V
IH
min FWH INIT# pin
specification. The 6300ESB inactive state of this signal is typically governed by the formula:
V_CPU_IO min - noise margin
≥
V
IH
min
Therefore, if the V_CPU_IO min of the processor is 1.6 V, the noise margin is 200 mV and the V
IH
min spec of the FWH INIT# input signal is 1.35 V, there would be no compatibility issue because
1.6 V - 0.2 V = 1.40 V which is greater than the 1.35 V minimum of the FWH. If the V
IH
min of the
FWH was 1.45 V, then there would be an incompatibility and level translation would need to be
used. These examples do not take into account actual noise that may be encountered on INIT#.
Care must be taken to ensure that the V
IH
min. specification is met with ample noise margin.
The following solutions assume that level translation is necessary. The figure below implements
the INIT# signal UP (
Figure 132 ) topology solution for the 6300ESB, FWH and the CPU. The
level translator circuitry is shown in Figure 133 .