158
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
6.1.6
HSYNC and VSYNC Design Considerations
HSYNC and VSYNC signals are connected to the analog display attached to the VGA connector.
These are 3.3 V outputs from the GMCH. A 39
Ω
series resistor is required before routing to the
VGA connector. Also, capacitors (28 pF to 33 pF) before and after the series resistor may be
needed to meet the VESA rise/fall time specification.
Unidirectional buffers (high impedance buffers) are required on both HYSNC and VSYNC to
prevent potential electrical overstress and illegal operation of the GMCH, since some display
monitors may attempt to drive HSYNC and VSYNC signals back to GMCH.
6.1.7
DDC and I
2
C Design Considerations
DDCADATA and DDCACLK are 3.3 volt IO buffers connecting the GMCH to the monitor. To
avoid potential electrical overstress on these signals, bidirectional level-shifting devices are
required. These signals require 2.2 k
Ω
pull-ups (or pull-ups with the appropriate value derived
from simulation) on each of these signals. Refer to
for further pull-up
recommendations for the DDC (GPIO) signal group.
6.2
LVDS Transmitter Interface
The Intel
®
LVDS (Low Voltage Differential Signaling) transmitter serializer converts up to 18 bits
of parallel digital RGB data, (6 bits per RGB), along with up to 4 bits for control (SHFCLK,
HSYNC, VSYNC, DE) into two 4 channel serial bit streams for output by the LVDS transmitter.
The transmitter is fully differential and utilizes a current mode drive with a high impedance output.
The drive current develops a differential swing in the range of 250 mV to 450 mV across a 100
Ω
termination load.
The parallel digital data is serially converted to a 7-bit serial bit stream that is transmitted over the
8-channel LVDS interface at 7x the input clock. The differential output clock channel transmits the
output clock at the input clock frequency. While the differential output channels transmit the data at
the 7x clock rate (1 bit time is 7x the input clock). The 7x serializer synchronizes and regenerates
an input clock from 35 MHz to 112 MHz. Typical operation is at 65 MHz (15.4 ns), therefore, at a
7x clock rate, 1bit time would be 2.2 ns. With data cycle times as small as 2.2 ns, propagation delay
mismatch is critical, such that intra-channel skew (skew between the inverting and non-inverting
output) must be kept minimal.
The following differential signal groups comprise the LVDS interface. The topology rules for each
group are defined in subsequent sections.
Table 44. Signal Group and Signal Pair Names
Channel
Signal Group
Signal Pair Names
Channel A
Clocks
ICLKAM, ICLKAP
Data Bus
IYAM[3:0],
IYAP[3:0]
Channel B
Clocks
ICLKBM, ICLKBP
Data Bus
IYBM[3:0],
IYBP[3:0]
Summary of Contents for 6300ESB ICH
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