Intel 6300ESB ICH, Design Manual

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January 2007 145
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Figure 72. Topology Command Signal to Clock Trace Length Matching Diagram
DIMM0
GMCH Package
SMA[12:6,3,0]
SBA[1:0],
SRAS#, SCAS#,
SWE
#
SCK[2:0]
SCK#[2:0]
Note: All lengths are measured from GMCH die
pad to DIMM connector pad.
Clock Reference Length = X0
DIMM0
DIMM1
SCK[5:3]
SCK#[5:3]
Clock Ref Length = X1
CMD Length = Y0
(X0 – 1.5")
≤
Y0
≤
(X0 + 1.0")
CMD Length = Y1
(X1 –1.5")
≤
Y1
≤
(X1 +1.0")
GMCH Package
Note: All lengths are measured from GMCH die
pad to DIMM connector pad.
855GME
GMCH
Die
SBA[1:0],
SRAS#, SCAS#,
SWE
#
SMA[12:6,3,0]
855GME
GMCH
Die