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Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - SPECIFICATION UPDATE 01-2011, Specification

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Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - SPECIFICATION UPDATE 01-2011 Specification Download Page 39

Specification Update

39

Specification Changes

The Specification Changes listed in this section apply to the following documents:

• Intel

®

 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic 

Architecture

• Intel

®

 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: 

Instruction Set Reference Manual A-M

• Intel

®

 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: 

Instruction Set Reference Manual N-Z

• Intel

®

 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: 

System Programming Guide

• Intel

®

 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: 

System Programming Guide

There are no new Specification Changes in this Specification Update revision.

Summary of Contents for 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - SPECIFICATION UPDATE 01-2011

Page 1: ...Reference Number 324643 001 2nd Generation Intel Core Processor Family Desktop Specification Update January 2011...

Page 2: ...y be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt...

Page 3: ...Specification Update Contents Revision History 5 Preface 6 Summary Tables of Changes 8 Identification Information 12 Errata 14 Specification Changes 37 Specification Clarifications 38 Documentation C...

Page 4: ...Contents 4 Specification Update...

Page 5: ...Specification Update 5 Revision History Revision Description Date 001 Initial Release January 2011...

Page 6: ...Volume 2 324642 001 Document Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor applnots 241618 htm Intel 64 and IA 32 A...

Page 7: ...of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be i...

Page 8: ...Document change or update will be implemented Plan Fix This erratum may be fixed in a future stepping of the product Fixed This erratum has been previously fixed No Fix There are no plans to fix this...

Page 9: ...X X No Fix LER MSRs May Be Unreliable BJ19 X X No Fix LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode BJ20 X X No Fix MCi_Status Overflow Bit May Be Incorrect...

Page 10: ...Duty Cycle Cannot be Programmed to 6 25 BJ46 X X No Fix Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX vvvv May Produce a NM Exception BJ47 X X No Fix Memory Aliasing of Code...

Page 11: ...g May Result in a Processor Hang BJ70 X X No Fix PerfMon Event LOAD_HIT_PRE SW_PREFETCH May Overcount BJ71 X X No Fix Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a NM Exception BJ72...

Page 12: ...the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Numb...

Page 13: ...sor Graphics Frequency Max Intel Turbo Boost Technology 2 0 Frequency GHz 1 Shared L3 Cache Size MB Notes SR008 i5 2500K D 2 000206a7h 3 3 1333 850 4 core 3 4 3 core 3 5 2 core 3 6 1 core 3 7 6 4 6 SR...

Page 14: ...core 2 4 3 core 2 8 2 core 3 2 1 core 3 3 6 3 4 5 6 SR00C i7 2600K D 2 000206a7h 3 4 1333 850 4 core 3 5 3 core 3 6 2 core 3 7 1 core 3 8 8 2 4 6 SR00B i7 2600 D 2 000206a7h 3 4 1333 850 4 core 3 5 3...

Page 15: ...er s Manual the use of MOV SS POP SS in conjunction with MOV r e SP r e BP will avoid the failure since the MOV r e SP r e BP will not generate a floating point exception Developers of debug tools sho...

Page 16: ...ers software may see load operations execute out of order Implication Memory ordering may be violated Intel has not observed this erratum with any commercially available software Workaround Software s...

Page 17: ...breakpoint enable flags are disabled DR7 G0 G3 and DR7 L0 L3 the DR6 B0 B3 flags may be incorrect Implication The debug exception DR6 B0 B3 flags may be incorrect for the load if the corresponding bre...

Page 18: ...May Result in Unexpected Values on Stack Frame Problem The ENTER instruction is used to create a procedure stack frame Due to this erratum if execution of the ENTER instruction results in a fault the...

Page 19: ...than 15 Bytes May be Preempted Problem When the processor encounters an instruction that is greater than 15 bytes in length a GP is signaled when the instruction is decoded Under some circumstances t...

Page 20: ...ode it is possible to get an Alignment Check Exception AC on the IRET instruction even though alignment checks were disabled at the start of the IRET This can only occur if the IRET instruction is ret...

Page 21: ...an incorrectly set the Overflow bit 62 in the MCi_Status register A DTLB error is indicated by MCA error code bits 15 0 appearing as binary value 000x 0000 0001 0100 in the MCi_Status register Implica...

Page 22: ...r during probe mode Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ24 Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions...

Page 23: ...apped to WB memory type by the MTRRs Status For the steppings affected see the Summary Tables of Changes BJ27 Single Step Interrupts with Floating Point Exception Pending May Be Mishandled Problem In...

Page 24: ...injection of a virtual NMI which is virtually asynchronous The erratum may affect VMMs relying on deterministic delivery of the affected VM exits Workaround None identified Status For the steppings af...

Page 25: ...es the upstream component to maintain the PCIe link at the target link speed or the highest speed supported by both components on the link whichever is lower PCIe root port will not initiate the link...

Page 26: ...undary in Code That Uses 32 Bit Address Size in 64 bit Mode Problem The FP Floating Point Data Operand Pointer is the effective address of the operand associated with the last non control FP instructi...

Page 27: ...rupts May be Generated From the Intel VT d Remap Engine Problem If software clears the F Fault bit 127 of the Fault Recording Register FRCD_REG at offset 0x208 in Remap Engine BAR by writing 1b throug...

Page 28: ...t branch after a transition of EIST T states S states C1E or Adaptive Thermal Throttling Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ44 VMREAD VMWR...

Page 29: ...VEX prefix to 1111b for instances of the VAESIMC and VAESKEYGENASSIST instructions Status For the steppings affected see the Summary Tables of Changes BJ47 Memory Aliasing of Code Pages May Cause Unpr...

Page 30: ...CIe devices Workaround None identified Status For the steppings affected see the Summary Tables of Changes BJ49 Unexpected UD on VZEROALL VZEROUPPER Problem Execution of the VZEROALL or VZEROUPPER ins...

Page 31: ...9BH with a VEX opcode extension should produce a UD Invalid Opcode exception Due to this erratum if CR0 MP and CR0 TS are both 1 the processor may produce a NM Device Not Available exception if one o...

Page 32: ...for the linear region Implication Due to this erratum an unexpected machine check with error code 0150H may occur possibly resulting in a shutdown Intel has not observed this erratum with any commerci...

Page 33: ...s affected see the Summary Tables of Changes BJ59 XSAVE Executed During Paging Structure Modification May Cause Unexpected Processor Behavior Problem Execution of XSAVE may result in unexpected behavi...

Page 34: ...ult reason 21H is not reported and instead the request uses the IRTE interrupt remapping table entry indexed by the low 16 bits of the interrupt index Workaround Software can use requestor id verifica...

Page 35: ...re Developer s Manual for recommendations for software treatment of asynchronous paging structure updates Status For the steppings affected see the Summary Tables of Changes BJ66 TSC Deadline Not Arme...

Page 36: ...ution of GETSEC instruction Intel has not been observed this erratum with any commercially available software Workaround None Identified Status For the steppings affected see the Summary Tables of Cha...

Page 37: ...Overflows May be Discarded Problem Under specific internal conditions when using Freeze PerfMon on PMI feature bit 12 in IA32_DEBUGCTL Freeze_PerfMon_on_PMI MSR 1D9H if two or more PerfMon Fixed Coun...

Page 38: ...workaround for this erratum Status For the steppings affected see the Summary Tables of Changes BJ77 An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 Problem If the fixed fun...

Page 39: ...oftware Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32...

Page 40: ...ectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64...

Page 41: ...IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Cha...

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