Troubleshooting Guide
1000BASE-T/100BASE-TX/10BASE-T Physical Layer Compliance Tests Manual
128
Intel Confidential
Figure G-3. Possible problems arising from duty cycle distortion. Each pulse above is meant
to be two bit times.
Figure 3 gives an idea of what could happen. Depending on the algorithm the receiver uses to
detect the signal levels each bit time, it may decide that the first pulse above is only 1 bit instead of
2, and/or it may decide that the negative pulse is 3 bits instead of two. Thus, problems may only
appear when transmitting to certain receive partners (with different Phy’s).
If a crystal is being used, check that the loading capacitors are correct and are of equal values.
G.10
Transmit Jitter (ANSI specification 9.1.9)
Transmit jitter causes problems for the receiving unit because it becomes more difficult to
distinguish the value of bits as jitter increases. Systems with excessive jitter will therefore cause the
receiving unit to have high Bit Error Rates.
There are several causes of jitter that can be addressed in board design and layout. Noisy boards
and poor common mode rejection will increase jitter. The noise can be made even worse by running
high speed traces near the network controller or in parallel with the differential traces. To reduce
noise, try as much as possible to maximize ground fill under the chip. Also make sure there is
adequate decoupling between V
CC
and Ground around the networking chip and around other chips
that may add noise to V
CC
. A metal top layer with several large via’s down to the ground plane
can reduce the problem.
0 V
Time
14 ns
18 ns
16 ns (2 Bit Times)
16 ns (2 Bit Times)
