User Manual 500 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Figure 115
PMBus block diagram
The PMBus module manages the I
2
C/SMBus/PMBus transactions by using a CPU. The advantage of such an
approach is to have a fully programmable, configurable, and extensible SMBus/PMBus interface that can
support any kind of commands. The PMBus module is partitioned into three main blocks:
•
PMB_I2CF block
•
PMB_APB block
•
PMB_FSM block
The PMBus module operation is enabled by enabling the dedicated kernel clock (pmbus_kernel_clk), by
releasing the dedicated peripheral reset signal (pmbus_rst_n), by properly configuring the module registers
through the APB interface, and by enabling the PMBus PHY to operate.
The PMB_I2CF block (I
2
C input signal formatter) has the duty to provide the debounced input signals,
“sda_in”
and “scl_in”, and the signals indicating input signal status change, to th
e PMB_FSM block (PMBUS PHY FSM).
The length of the debouncing can be configured through the APB register. The PMB_I2CF also provides the
“transaction_in_progress” signal
, indicating when an I
2
C/PMBus transaction is in progress (signal will be
asserted from the start event until the stop event). Finally, the PMB_I2CF operates only when the PHY is
enabled.
The PMB_APB block implements the APB interface and contains all the CPU registers required to control and
manage the PMBus interface (i.e., the PMB_FSM and the PMB_I2CF). The PMB_APB is also in charge of asserting
and deasserting the SMBALERT signal. The PMB_APB embeds the logic to manage the service request
generated by the PMB_FSM. Finally, the PMB_APB embeds a selectable feature to manage the ACK/NACK
response without the need to stretch the clock.
The PMB_FSM block implements the state machine to support the I
2
C physical layer communication. The
PMB_FSM machine is fully controlled by the CPU. The PMB_FSM is also in charge of accommodating the signal
crossing clock domains due to the presence of the dedicated PMBus PHY clock (pmbus_kernel_clk). As far as
the clock domains go, it is assumed that all required clocks, even with different frequencies, are synchronous
with each other. A WDT is provided to monitor the SCL low status per SMBus specification; another WDT is
PMBUS_TOP
PMBUS_APB
I2CF
SCL_IN
SDA_IN
A
P
B
I
F
P
M
B
U
S
IF
FSM
SCL_IN_F
SDA_IN_F
SCL_OUT
SDA_OUT
Irq_bus
fsm_stat
fsm_ctrl
fsm_cnfg
clr_irq
i2c
f_
cn
fg
