User Manual 490 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
GPIOPCellID2
GPIOPCellID2
R
6004_0FF8h
6005_0FF8h
[7:0]
CellID[23:16]. Together with the
other cell ID registers, CellID[31:0] is
used as a standard cross-peripheral
ID system. In this case CellID[31:0] =
0xB105F00D.
GPIOPCellID3
GPIOPCellID3
R
6004_0FFCh
6005_0FFCh
[7:0]
CellID[31:24]. Together with the
other cell ID registers, CellID[31:0] is
used as a standard cross-peripheral
ID system. In this case CellID[31:0] =
0xB105F00D.
15.8
WDT module
The watchdog block is an Arm® IP cell from the Arm® AMBA® Design Kit; extensive documentation can be found
in the
“
Arm® AMBA® Design Kit
Technical Reference Manual”, paragraph 4.4 “Watchdog unit”.
The watchdog module is based around a 32-bit downcounter that is initialized from the reload register,
WDOGLOAD.
The watchdog clock generates a regular interrupt, WDOGINT, depending on a programmed value. The counter
decrements by one on each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is high. The
watchdog asserts an interrupt when the counter reaches zero, then reloads the counter and starts another
downcount. If the interrupt is not cleared by the time the counter next reaches zero, then the watchdog module
asserts the reset signal.
The watchdog module is intended to be used to apply a reset to a system in the event of a software failure,
providing a way of recovering from software crashes.
The watchdog unit has a protection mechanism for which registers are locked (not writable), to protect its
integrity in case of FW malfunctioning events. Protection is entered using the password register.
The watchdog unit can be enabled or disabled as required.
