User Manual 391 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
The ROM memory BIST is a HW engine used during chip production to verify the proper functionality of the
module (self-check functional test). It reads the entire content of the ROM, generating a signature that is
checked for correctness.
The ROM AHB wrapper implements the protocol layer to the AMBA® AHB bus. ROM access time is zero wait
state.
The ROM module is used by the Arm® Cortex®-M0 for code boot repository and execution. On power-up, the
Cortex®-M0 starts to execute code from the first ROM location.
15.4.2
Random-access memory
The random-access memory (RAM) space consists of two identical instances of RAM modules. Each module has
its own AHB access port, enabling simultaneous access to different memories, through the bus matrix, by the
two system masters (Cortex®-M0 and DMA).
Each RAM module embeds an AHB wrapper, the SRAM BIST, and the SRAM memory macro.
Each SRAM macro features a 16 kB SRAM; it is organized into 4K lines x 32 bits and it allows byte, half-word and
word access.
The SRAM memory BIST is a HW engine used during production to verify the proper functionality of the module
(self-check functional test). It reads and writes every memory cell macro using a specific algorithm
(checkboard, MARCH2) to detect physical defects.
The RAM AHB wrapper implements the protocol layer to the AMBA® AHB bus. RAM access time is zero wait state
on single READ/WRITE and single-cycle wait state on a sequence WRITE followed by a READ.
The RAM space is used by the Arm® Cortex®-M0 for handling FW variables, fast code execution and data storage.
15.4.3
One-time programmable memory
The one-time programmable (OTP) module is a block to access, configure, and test the SiPROM macro.
TheSiPROM macrocell is an embedded NVM IP core providing OTP or emulated multiple-time programmable
capability. OTP macro size is 512K bits, with a 128-bit data bus access (4K x 128-bit data organization).
OTP module interconnections are Arm® Cortex®-M0 oriented (32-bit data bus), with an AHB direct interface (not
burst capable, with read-only access to OTP macro data) and an APB register interface for configuration,
indirect access (to read and write/program OTP) and test. AHB and APB bus interfaces are defined according to
Arm® AMBA® specification Rev 2.0 (ARM IHI 0011A).
The OTP block diagram is shown in
