User Manual 390 of 562 V 1.0
2021-08-25
XDPP1100 technical reference manual
Digital power controller
Central processing unit subsystem
Register name Field name
Access Address
Bits
Description
RSTMODS_CLR DTIMER3RST
W
4000_1024h [13]
D
TIMER3
module reset bit. To exercise
a module reset, FW has to set and
clear the proper bit accordingly.
0: Status of module reset
unchanged
1: Release reset
RSTMODS_CLR WDTIFRST
W
4000_1024h [14]
WDT module reset bit. To exercise a
module reset, FW has to set and
clear the proper bit accordingly.
0: Status of module reset
unchanged
1: Release reset
RSTMODS_CLR GPIO0RST
W
4000_1024h [15]
GPIO0 module reset bit. To exercise
a module reset, FW has to set and
clear the proper bit accordingly.
0: Status of module reset
unchanged
1: Release reset
RSTMODS_CLR GPIO1RST
W
4000_1024h [16]
GPIO1 module reset bit. To exercise
a module reset, FW has to set and
clear the proper bit accordingly.
0: Status of module reset
unchanged
1: Release reset
15.4
Memory
XDPP1100 contains three different memory types: ROM, RAM and OTP. They provide the infrastructure to:
•
Store the application code
•
Provide an execution space
•
Support configurability and trimming parameters
•
Support a code patching mechanism
ROM and RAM are Infineon Technologies macros, highly optimized for area and power.
OTP is a NVM external IP provided by a third party.
15.4.1
Read-only memory
The read-only memory (ROM) module embeds an AHB wrapper, the ROM memory BIST and the ROM memory
macro.
The ROM macro features 80 kB and is organized into 20K lines x 32 bits.
