Technical Reference Manual
002-29852 Rev. *B
23.9.51 SCB_INTR_RX_MASK
Description:
Receiver interrupt mask
Address:
0x40600FC8
Offset:
0xFC8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits
7
6
5
4
3
2
1
0
Name
BLOCKED
[7:7]
UNDERFLOW
[6:6]
OVERFLOW
[5:5]
None [4:4]
FULL [3:3]
NOT
_EMPTY
[2:2]
None [1:1]
TRIGGER
[0:0]
Bits
15
14
13
12
11
10
9
8
Name
None [15:12]
BREAK
_DETECT
[11:11]
BAUD
_DETECT
[10:10]
PARITY
_ERROR
[9:9]
FRAME
_ERROR
[8:8]
Bits
23
22
21
20
19
18
17
16
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
Name
None [31:24]
Bit-fields
Bits Name
SW
HW
Default or
Enum
Description
0
TRIGGER
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
2
NOT_EMPTY
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
3
FULL
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
5
OVERFLOW
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
6
UNDERFLOW
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
7
BLOCKED
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
8
FRAME_ERROR
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
9
PARITY_ERROR
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
10
BAUD_DETECT
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
11
BREAK_DETECT
RW
R
0
Mask bit for corresponding bit in interrupt request
register.
1453
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers