Firmware User Manual (AE-step)
16
Revision 1.02
2019-04-24
TLE984x Firmware User Manual
BootROM Startup procedure
• RAM Test (MBIST) and RAM initialization
• Analog module trimming
• Startup Error Handling
• No Activity Counter (NAC) Configuration
• Node Address for Diagnostics (NAD) Configuration
3.8.1
Watchdog Configuration
After a reset, the watchdog WDT1starts with a long open window. For all the reset types, firmware startup in
user mode enables WDT1 before jumping to user code, and the watchdog cannot be disabled while user code
is being executed.
The watchdog WDT1is disabled before entering into debug mode. WDT1 continues running while waiting for
the first BSL frame. If host synchronisation is completed during the BSL waiting time (defined by NAC), WDT1
is disabled and its status is frozen.
WDT1 continues running while waiting for the first BSL frame. If host synchronisation is completed during the
BSL waiting time (defined by NAC), WDT1 is disabled and its status is frozen.
3.8.2
RAM Test (MBIST) and RAM Initialization
The RAM memory test is performed for cold reset type.
The RAM initialization is performed for cold and warm reset types.
It is possible to force a RAM test and the RAM initialization for the whole RAM range during startup regardless
of reset type. This can be done by enabling the feature using the user API function
. Exception for the forced test is that for WARM reset the first 1kB of the RAM will not be checked.
User_ram_mbist() must therefore be called by the user on the first 1kB RAM range to make sure RAM test and
RAM initialization is performed and no errors exist (user_ram_mbist(0x18000000, 0x180003FF) ).
When executed, the RAM MBIST test destroys the contents of the tested RAM. It consists of a linear write/read
algorithm using alternating data. RAM MBIST execution is user configurable for all reset types, see
Prior to calling MBIST to test the first 1kB of RAM, stack and variables must be moved to the already tested RAM
range above 1kB.
In case an error is detected in the RAM MBIST, the appropriate error status is captured and the device enters
an endless loop. As the watchdog is enabled when entering the endless error loop after a boot in user or
debugmode, a WDT1 cold reset is asserted after timeout and the RAM test is re-executed.
After five (5) consecutive watchdog resets, the device enters SLEEP mode (by hardware function).
The RAM initialization writes the whole RAM to zero with the proper ECC status. This is needed to prevent an
ECC error during user code execution due to a write operation to a non initialized location (with invalid ECC
code).
Note: The standard RAM interface is disabled during MBIST test execution.
