Infineon TLE984 QX Series User Manual Download

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User Manual

775

Rev. 1.1

2019-03-18

TLE984xQX

Microcontroller with LIN and Power Switches for Automotive Applications

10-Bit Analog Digital Converter (ADC1)

Measurement Unit 1 Channel Enable Bits for Cycle 4-5

ADC1_SQ4_5

Offset

Reset Value

Measurement Unit 1 Channel Enable Bits for
Cycle 4-5

see

Table 420

Field

Bits

Type

Description

RES

31:28

Reserved

Always read as 0

SQ5

27:16

Sequence 5 channel enable

The following values can be ored:
0000 0000 0001

CH0_EN

, Channel 0 enable

0000 0000 0010

CH1_EN

, Channel 1 enable

0000 0000 0100

CH2_EN

, Channel 2 enable

0000 0000 1000

CH3_EN

, Channel 3 enable

0000 0001 0000

CH4_EN

, Channel 4 enable

0000 0010 0000

CH5_EN

, Channel 5 enable

0000 0100 0000

CH6_EN

, Channel 6 enable

0000 1000 0000

CH7_EN

, Channel 7 enable

0001 0000 0000

CH8_EN

, Channel 8 enable

0010 0000 0000

CH9_EN

, Channel 9 enable

0100 0000 0000

CH10_EN

, Channel 10 enable

1000 0000 0000

CH11_EN

, Channel 11 enable

RES

15:12

Reserved

Always read as 0

RES

SQ5

RES

SQ4

Summary of Contents for TLE984 QX Series

Page 1: ...er with detailed descriptions about the behavior of the TLE984xQX functional units and their interaction The manual describes the functionality of the superset device of the TLE984xQX Embedded Power I...

Page 2: ...1 Power Supply Generation Register 42 6 3 6 2 VDDEXT Control Register 46 6 4 Power Control Unit 48 6 4 1 Power Control Unit Fail Safe Scenarios 48 6 4 1 1 Power Supervision Function of PCU 48 6 4 1 2...

Page 3: ...illator OSC_PLL 97 7 3 3 6 Switching PLL Parameters 97 7 3 3 7 Oscillator Watchdog Event or PLL Loss of Lock Detection 98 7 3 3 8 Oscillator Watchdog Event or Loss of Lock Recovery 98 7 3 4 Clock Cont...

Page 4: ...igger 192 7 8 1 1 Differential Unit Trigger register 192 7 9 Flexible Peripheral Management 195 7 9 1 Peripheral Management Registers 196 7 10 Module Suspend Control 198 7 11 Baud rate Generator 200 7...

Page 5: ...252 9 3 1 1 General Purpose Registers 252 9 3 1 2 Special Purpose Registers 252 9 4 Summary of Processor Registers 254 9 5 Instruction Set Summary 282 10 Address Space Organization 285 11 Memory Contr...

Page 6: ...e 3 ADC10 318 13 3 1 4 Interrupt Node 4 5 6 7 CCU6 319 13 3 1 5 Interrupt Node 8 and 9 SSC 320 13 3 1 6 Interrupt Node 10 UART1 321 13 3 1 7 Interrupt Node 11 UART2 322 13 3 1 8 Interrupt Node 12 and...

Page 7: ...ister Description 401 15 4 2 Port 1 412 15 4 2 1 Overview 412 15 4 2 2 Port 1 Functions 412 15 4 2 3 Port 1 Register Description 415 15 4 3 Port 2 425 15 4 3 1 Overview 425 15 4 3 2 Port 2 Functions 4...

Page 8: ...tion of the GPT12 Module 493 16 6 1 Module Connections 493 17 Timer2 and Timer21 496 17 1 Features 496 17 2 Introduction 496 17 2 1 Timer2 and Timer21 Modes Overview 496 17 3 Functional Description 49...

Page 9: ...3 Shadow Register Transfer 547 18 5 Trap Handling 549 18 6 Multi Channel Mode 551 18 7 Hall Sensor Mode 553 18 7 1 Hall Pattern Evaluation 554 18 7 2 Hall Pattern Compare Logic 556 18 7 3 Hall Mode Fl...

Page 10: ...0 19 9 Interfaces of the UART Module 641 20 LIN Transceiver 643 20 1 Features 643 20 2 Introduction 643 20 2 1 Block Diagram 645 20 3 Functional Description 645 20 3 1 LIN Normal Mode 645 20 3 2 LIN T...

Page 11: ...22 6 Supplement Modules 687 22 6 1 Functional Safety Concept 687 22 6 2 Supplement Modules Control and Status Register 688 23 Measurement Core Module incl ADC2 690 23 1 Features 690 23 2 Introduction...

Page 12: ...iption 800 24 7 1 1 Step Response 801 24 7 2 IIR Filter Control Registers 803 24 8 Signal Processing 844 24 8 1 Functional Description 844 24 8 2 Postprocessing Control Registers 846 24 9 Interrupt Ha...

Page 13: ...3 Overtemperature Detection 949 27 2 2 Operation of Low Side Switch in PWM Mode 949 27 2 2 1 Application Requirement for Low Side Switch in PWM Mode 951 27 3 Register Definition 952 27 3 1 Low Side Sw...

Page 14: ...ct variant dependant High Voltage Monitor Input pins for wake up and with cyclic sense with analog measurement option 10 General purpose I O Ports GPIO 6 Analog input Ports 10 Bit A D Converter with 6...

Page 15: ...e Low Side Loss of clock detection with fail safe mode for power switches Temperature Range TJ 40 C up to 150 C Package VQFN 48 31 with LTI feature Green package RoHS compliant AEC Qualified 1 1 TLE98...

Page 16: ...pose Input Output HV High Voltage ICU Interrupt Control Unit LDO Low DropOut voltage regulator LIN Local Interconnect Network LSB Least Significant Bit LTI Lead Tip Inspection LV Low Voltage MCU Micro...

Page 17: ...y SCU System Control Unit SOW Short Open Window for WDT1 SPI Serial Peripheral Interface SSC Synchronous Serial Channel SWD Arm Serial Wire Debug TCCR Temperature Compensation Control Register TMS Tes...

Page 18: ...TEST DEBUG INTERFACE ARM CORTEX M0 FLASH SRAM ROM Multilayer AHB Matrix PBA0 ADC10B LS1 PMU Power Management Unit 1 5 MON PBA1 UART1 SSC1 T21 SCU_DM PLL GPIO P0 x P1 x P2 x ANx MON 1 5 MU DPP2 LIN VDD...

Page 19: ...nout vsd E P2 1 37 13 GNDLS 24 P0 4 2 5 P0 5 3 6 P2 3 E E E L S1 11 N C 10 M ON 5 N U 9 M ON 4 8 M ON 3 7 M ON 2 6 M ON 1 5 HS2 N U 4 HS1 3 GNDL IN 2 L IN 1 14 P1 0 15 P1 1 16 P1 2 17 P0 1 18 TMS SWD...

Page 20: ...lternate functions can be assigned and are listed in the Port description Main function is listed below P0 0 20 I O I PU SWD_CLK GPIO Serial Wire Debug Clock General Purpose IO Alternate function mapp...

Page 21: ...I O I Hi Z XTAL21 Alternate function mapping see Table 232 External oscillator output P2 6 34 I I AN6 ADC1 analog input channel 10 Alternate function mapping see Table 232 P2 7 35 I I AN7 ADC1 analog...

Page 22: ...High Side Switch output 2 product variant dependant LIN Interface LIN 1 I O PU LIN bus interface input output Others TMS 18 I I PD TMS SWD_IO test mode select input Serial Wire Debug input output RESE...

Page 23: ...ntrolled by a programmable window watchdog A cyclic wake up circuit supply voltage supervision and integrated temperature sensors are available on chip All relevant modules offer power saving modes in...

Page 24: ...up from this mode is possible by LIN bus activity or the High Voltage Monitor Input pins and cyclic wake A wake up from Sleep Mode behaves similar to a power on reset While changing into Sleep Mode no...

Page 25: ...triggered by rising falling or both signal edges for each monitor input individually LSx ON OFF OFF OFF LIN TRx ON OFF wake up only OFF wake up only OFF MONx wake up n a disabled static cyclic disabl...

Page 26: ...ite 0 rwh1 write onlyfromSW SetbySW for 1 cycle then reset by HW no yes no yes no rwhir rw from SW can be reset by HW yes yes no yes covered by SW write rwhis rw from SW can be set by HW yes yes yes n...

Page 27: ...tection has been opened for 32 cycles yes yes but gated by PASSWD protection no no covered by SW write w clear on write 1 for interrupts interruptstatusclearbit and sticky status registers status clea...

Page 28: ...ystem IC Therefore the power management unit controls all system modes including the corresponding transitions The power management unit is responsible for generating all needed voltage supplies for t...

Page 29: ...ckup Clock Source for System Clock Source for WDT1 This ultra low power oscillator generates the clock for the PMU This clock is also used as backup clock for the system in case of PLL Clock failure a...

Page 30: ...ontrol Unit of the PMU This block is responsible for controlling all power related actions within the PGU Module It also contains all regulator related diagnosis like under and overvoltage detection o...

Page 31: ...Chapter Power Control Unit Fail Safe Scenarios the power save modes are set by the user software only The PMU gets the respective command and after a certain delay the corresponding ready signal will...

Page 32: ...LIN dominant pulse or a corresponding rising edge falling edge activity at the MON input These events are triggered outside of the PMU The PMU itself processes the wake up information in an independe...

Page 33: ...ming The wake up procedure from Sleep Mode via MONx pins instead of LIN follows the same sequence as shown in the figure above Stop Mode The objective of the Stop Mode is to provide a data retention f...

Page 34: ...e corresponding limitation is given by the external buffer capacitor at the VDDC VDDP pin In case of a 330 nF buffer capacitor at VDDC the allowable load jump is 300 A ms The figure below shows the St...

Page 35: ...for Stop exit and Sleep exit same XSFR Generally the synchronous wake up features are equivalent to the Sleep Mode exit The Stop Mode terminates by using one of the synchronous wake up features The sy...

Page 36: ...ment Unit PMU sensing time the PMU evaluates the corresponding GPIO In case of a valid wake up signal the PMU goes to Active Mode and the application software takes control over the system If no valid...

Page 37: ...ionfor the following regulator stages VDDP 5V digital voltage regulator used for internal modules and all GPIOs VDDC 1 5V digital voltage regulator used for internal microcontroller modules and core l...

Page 38: ...signalling Interrupt Undervoltage monitoring with Reset Undervoltage Reset VDDPUV Overtemperature shutdown with MCU signalling Interrupt Pre Regulator for VDDC Regulator GPIO Supply Pull Down Current...

Page 39: ...monitoring and Shutdown with MCU signalling Interrupt Overvoltage monitoring with MCU signalling Interrupt Undervoltage monitoring with MCU signalling interrupt Undervoltage monitoring with reset Ove...

Page 40: ...drive small capacitive loads Intrinsic current limitation Undervoltage monitoring and shutdown with MCU signalling Interrupt Overtemperature Shutdown with MCU signalling Interrupt Pull Down Current S...

Page 41: ...itches for Automotive Applications Power Management Unit PMU 6 3 4 Power on Reset Concept Figure 14 Power on Reset Concept Vs 1 5V PMU_1V5DidPOR 5V VDDP 3V SYSTEM_STATE Active Down LP_Clk 1 5V VDDC 80...

Page 42: ...the overvoltage and overload condition of VDDP and VDDC To use this information as interrupt sources it must be selected explicitly in this register Table 7 Register Address Space for PMU Registers Mo...

Page 43: ...time of 290 us typ is passed the system will be puttosleepmode Thisflagisautomatically cleared if error condition is removed 0B No overload 1B Overload PMU_5V_OVERVOLT 4 r Overvoltage at VDDP regulato...

Page 44: ...pmode Thisflagisautomatically cleared if error condition is removed 0B No overload 1B Overload PMU_1V5_OVERVOLT 0 r Overvoltage at VDDC regulator Note This flag is automatically cleared if error condi...

Page 45: ...8 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Power Management Unit PMU Figure 15 VDDP VDDP_OV_PREWARN VPPD_OV UV_PREWARN VDDP V VDDP_UV_PREWARN UV Reset Threshol...

Page 46: ...otive Applications Power Management Unit PMU Figure 16 VDDC 6 3 6 2 VDDEXT Control Register The VDDEXT can be fully controlled by the following SFR Register including all diagnosis functions VDDC_OV_P...

Page 47: ...re not cleared RES 10 8 r Reserved Always read as 0 VDDEXT_STABLE 7 r VDDEXT Supply Stable 0B VDDEXT not in stable condition 1B VDDEXT in stable condition VDDEXT_OT 6 r VDDEXT Supply Overtemperature 0...

Page 48: ...re reset on RESET pin 6 4 1 1 Power Supervision Function of PCU The power supervision feature of the PCU is mainly responsible for monitoring the voltage regulators VDDP and VDDC In case of voltage re...

Page 49: ...reset the application software takes over the system control If the software doesn t service the system watchdog then the described procedure starts again After the watchdog is not serviced five time...

Page 50: ...by forcing the bidirectional reset pin The reset pin goes high again if the PMU releases the MCU reset This event is shown in the reset status register as a hard reset together with a wake up reset I...

Page 51: ..._FAIL is cleared Table 11 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition PMU System Fail Register PMU_HIGHSIDE_CTRL High Side Control Register...

Page 52: ...ates Overload Condition at VDDP 0B No Overload VDDP ok 1B Overload VDDP Overload PMU_1V5_OVL 2 rh VDDC Overload Flag Indicates Overload Condition at VDDC 0B No Overload VDDC ok 1B Overload Hall VDDC O...

Page 53: ...can be configured for rising edge triggered and falling edge triggered wake up events This setup can be used to wake up the device from Stop Mode with or without cyclic sense but also a wake up from...

Page 54: ...utomotive Applications Power Management Unit PMU 1 Port 2 pins cannot invoke any wake up 2 None of the GPIOs is supplied during Sleep Mode therefore wake up is not possible through them Figure 18 Bloc...

Page 55: ...Table 14 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition PMU Wake Up Configuration Register PMU_LIN_WAKE_EN LIN Wake Enable 050H 0000 0000H PMU_...

Page 56: ...19 03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Power Management Unit PMU 6 5 1 1 PMU Wake Up Configuration Register This register is dedicated for the contr...

Page 57: ...input for cycle sense enable 1B ENABLE input for cycle sense enabled 0B DISABLE input for cycle sense disabled CYC_0 16 rw GPIO1_0 input for cycle sense enable 1B ENABLE input for cycle sense enabled...

Page 58: ...p enabled 0B DISABLE wake up disabled RES 3 r Reserved Always read as 0 RI_2 2 rw Port 1_2 Wake up on Rising Edge enable 1B ENABLE wake up enabled 0B DISABLE wake up disabled RI_1 1 rw Port 1_1 Wake u...

Page 59: ...lter time for the Wake up 00B 10_us 10 s filter time 01B 20_us 20 s filter time 10B 40_us 40 s filter time 11B 5_us 5 s filter time CNF_MON_FT 1 rw Wake up Filter time for Monitoring Inputs Selects th...

Page 60: ...pe Reset Values Reset Short Name Reset Mode Note RESET_TYPE_2 00000000H RESET_TYPE_2 PMU_WAKE_STATUS Offset Reset Value Main wake status register 000H see Table 18 Field Bits Type Description RES 31 2...

Page 61: ...ister is cleared automatically by read operation The user has to clear this flag before entering power saving modes otherwise the device will stay in active 0B No wake up detected 1B wake up detected...

Page 62: ...y in active 0B No wake up detected 1B wake up detected RES 7 6 r Reserved Always read as 0 FAIL 5 r Wake up after VDDEXT Fail 0B No Wake up occurred 1B Wake up occurred CYC_WAKE 4 rh Wake up caused by...

Page 63: ...ster 004H see Table 19 Field Bits Type Description RES 31 20 r Reserved Always read as 0 RES 19 13 r Reserved Always read as 0 GPIO1_STS_4 12 rh Wake GPIO1_4 0B No wake up detected 1B wake up detected...

Page 64: ...QX Microcontroller with LIN and Power Switches for Automotive Applications Power Management Unit PMU Table 19 RESET of PMU_GPIO_WAKE_STATUS Register Reset Type Reset Values Reset Short Name Reset Mode...

Page 65: ...19 The sensing time where the enable signal is active will be set in the PMU_SLEEP The flags inside PMU_SLEEP register are used to configure the dead time TDead The PMU_SLEEP CYC_SENSE_S_DEL register...

Page 66: ...Timing Diagram for Cyclic Sense 6 6 1 1 Configuration of Cyclic Sense Mode The configuration of cyclic sense mode is shown in Figure 20 Timing_Diagram_Stop_Mode_Exit_Cyclic_Sense_Customer vsd Cycle Se...

Page 67: ...ion Flow of cyclic sense mode cyclic_sense_config vsd Wakeup hasoccurred Execute Highside CyclicSense Handover byenabling High Side Driver HS1_CTRL 8 h05 Sleep Mode No Yes Enable and turn on hsswitch...

Page 68: ...e Once the time interval is elapsed the PMU enters the Startup Mode and proceeds to Active Mode where the software takes over the system control The cyclic wake interval is set in the PMU_SLEEP XSFR 6...

Page 69: ...the cyclic mode is turned on to the sensing window where the wake inputs MONx GPIOx are sensed The delay time can be configured in the PMU_SLEEP CYC_SENSE_S_DEL register The sensing window is fixed t...

Page 70: ...ad as 0 CYC_WAKE_E01 21 20 rw Exponent 00B Exponent value is 0 01B Exponent value is 1 10B Exponent value is 2 11B Exponent value is 3 CYC_WAKE_M03 19 16 rw Mantissa Mantissa value is calculated as CY...

Page 71: ...yclic sense feature for the power save modes 0B Cyclic Sense disabled 1B Cyclic Sense enabled CYC_WAKE_EN 2 rw Enabling Cyclic Wake This bit enables the cyclic wake feature for the power save modes 0B...

Page 72: ...he minimum supply voltage for Active Mode Then the PMU starts the sequence to power up the supply generation module which ends with the release of the MCU reset If this status is reached then the embe...

Page 73: ...fication bit PMU_SleepEx is set instead of the power on identification bit Figure 22 Power Down and Power Loss Sequence In the default configuration the wake up from Stop Mode works without reset To w...

Page 74: ...ternal oscillator LP_CLK the PMU resets the MCU The prioritization of the described reset sources is done according to the architecture and the functionality of the embedded system itself The software...

Page 75: ...ulled down PMU_ExtWDT this reset is a WDT1 related reset PMU_SOFT this reset is a software related reset PMU_Wake this reset is a stop wake up related reset PMU_FAIL WDT_FAIL RESET_TYPE_3 is an OR of...

Page 76: ...PMU_RESET_STS The reset blind time envelopes the phase where the reset pin acts as an active reset output The functionality of the reset blind time is sketched below Figure 24 Reset blind time Note A...

Page 77: ...w Reset Pin Blind Time Selection Bits These bits select the blind time for the reset input sampling 00B RST_TFB_0 0 5 s typ 01B RST_TFB_1 1 s typ 10B RST_TFB_2 5 s typ 11B RST_TFB_3 31 s typ Table 23...

Page 78: ...te The register PMU_RESET_STS is also cleared when PMU_RESET_STS PMU_LPR is cleared PMU_RESET_STS Offset Reset Value Reset Status Register 010H see Table 24 Field Bits Type Description RES 31 11 r Res...

Page 79: ...Exit executed PMU_WAKE 1 rwh Flag which indicates a reset caused by Stop Exit Note Stop Exit with reset must be configured explicitly in the PMU_WAKE UP_CTRL register1 0B No reset caused by Stop Exit...

Page 80: ...Purpose User DATA0to3 Storage Register Table 25 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition Data Storage Registers PMU_GPUDATA0to3 General...

Page 81: ...0000H RESET_TYPE_1 PMU_GPUDATA4to7 Offset Reset Value General Purpose User DATA4to7 0C4H see Table 27 Field Bits Type Description DATA7 31 24 rw DATA7 Storage Byte 8th byte of storage area DATA6 23 16...

Page 82: ...te 12th byte of storage area DATA10 23 16 rw DATA10 Storage Byte 11th byte of storage area DATA9 15 8 rw DATA9 Storage Byte 10th byte of storage area DATA8 7 0 rw DATA8 Storage Byte 9th byte of storag...

Page 83: ...put output control Debug mode control of system peripherals 7 2 Introduction The System Control Unit SCU supports all central control tasks in the TLE984xQX The SCU is made up of the following sub mod...

Page 84: ...reset of power down supply PMU_PIN Reset generated by reset pin PMU_ExtWDT WDT1 reset PMU_SOFT Software reset PMU_Wake Stop Mode exit with reset SCU_DM_Block_Diagram_Cust vsd System ControlUnit Digita...

Page 85: ...dules SCU DM Reset_Type_3 Peripheral reset contains all resets Reset_Type_4 Peripheral reset without SOFT Baudrate generator fBR Baudrate clock for UART Port Control P0_POCONy PDMx driver strength con...

Page 86: ...e Table 61 SCU_VTOR Vector Table Reallocation Register 020H see Table 62 SCU_NMICON NMI Control Register 024H see Table 63 SCU_EXICON0 External Interrupt Control Register 0 028H see Table 64 SCU_EXICO...

Page 87: ...SCU_BG2 dedicatedfor UART2 Baud Rate Timer Reload Register 0A0H see Table 105 SCU_LINSCLR dedicated for UART1 LIN Status Clear Register 0A4H see Table 107 SCU_ID Identity Register 0A8H see Table 116 S...

Page 88: ...tatus Clear Register 10CH see Table 110 SCU_GPT12IEN General Purpose Timer 12 Interrupt Enable Register 15CH see Table 88 SCU_GPT12IRC Timer and Counter Control Status Register 160H see Table 79 SCU_I...

Page 89: ...put external clock signal to a high frequency internal clock The system clock fSYS is generated out of the following selectable clocks PLL clock output fPLL Direct clock from oscillator OSC_HP fOSC Di...

Page 90: ...must be connected to XTAL1 XTAL2 is left open unconnected 7 3 2 2 External Crystal Mode When using an external crystal its frequency can be within the range of 4 MHz to 6 MHz An external oscillator lo...

Page 91: ...neration PLL Loop filter Wide range of input frequencies divided by configurable P divider Wide VCO frequency tunning range VCO lock detection Oscillator run detection 4 bit VCO output frequency feedb...

Page 92: ...Mode Bypassing K1 divider and ignoring the P divider this defines the Freerunning Mode Table 3 shows the selectable clock source options Normal Mode In Normal Mode the reference frequency fR is divid...

Page 93: ...a factor K1 The output frequency is given by 7 2 The Prescaler Mode is selected by the following settings PLL_CON VCOBYP 1 PLL_CON OSCDISC X The Prescaler Mode is active when PLL_CON VCOBYP 1 PLL_CON...

Page 94: ...The following table shows the possible N loop division rates and gives the valid output frequency range for fREF depending on N and the VCO frequency range All not allowed combinations are related to...

Page 95: ...tput frequency of the VCO fVCO is divided by K2 to provide the final desired output frequency fPLL Table 36 shows the output frequency range depending on the K2 divisor and the VCO frequency range Not...

Page 96: ...ce clock the internal oscillator OSC_PLL frequency fINT is used and therefore the internal oscillator must be put into operation Table 37 K1 Divisor Table K1 fPLL for fR Duty Cycle 4 5 6 1 4 0 5 0 6 0...

Page 97: ...supervised using the OSC_PLL as reference frequency For more information see Section 7 3 3 3 7 3 3 6 Switching PLL Parameters The following restriction applies when changing PLL parameters via the PLL...

Page 98: ...In addition the lock flag is reset Note that in the first place the LOCK flag has to be set first before a loss of lock NMI request is generated This avoids a potential PLL loss of lock NMI request a...

Page 99: ...ules SCU DM 3 If desired re configure the PLL divider settings 4 Setting the restart lock detection bit PLL_CON RESLD 1 5 Waiting until the PLL VCO part becomes locked PLL_CON LOCK 1 6 When the LOCK i...

Page 100: ...t equals CPU clock must be same or higher TFILT_CLK for digital filtering in analog peripherals e g for comparators Should be configured to be at 2 MHz as close as possible Some peripherals are clocke...

Page 101: ...OSC Watchdog Timer CLKREL NVM COREL Toggle Latch TLEN M U X f SYS CLKOUT Clock Control Unit NVMACCCLK NVMCLKFAC NVMCLK COUTS1 f LP_CLK MI_CLK Measurement Interface APCLK1FAC Analog Subsystem PBA0 PBA...

Page 102: ...r CCU6 GPT12 PCLK SCU_PM WDT1 SCU_PM MI_CLK APCLK1FAC 1 2 3 4 MCU Registers Core PCLK CCLK APCLK1FAC LP_CLK APCLK2FAC APCLK2FAC 1 2 3 24 LP_CLK 1 2 Peripherals PCLK PBA0CLKREL SCU_PM CLKWDT CLKWDT2 CL...

Page 103: ...et With this reset the previous user configuration of PLL and clock system is retained across the reset Note In the event the PLL fails to lock during startup operation the LP_CLK continues to provide...

Page 104: ...s control the setting and trimming of OSC_PLL the Power Down of XTAL OSC_HP and the control and status monitor of oscillator watchdog OSC Control Register SCU_OSC_CON Offset Reset Value OSC Control Re...

Page 105: ...Reset Setting this bit will reset the OSC2L status flag to 1 and restart the oscillator detection This bit will be automatically reset to 0 and thus always be read back as 0 0B No effect 1B ResetOSC2...

Page 106: ...uld be written with 0 UNPROT_VCOBYP 11 w Unprotect write access of VCO_BYP Writing this Bit within an write access of VCO_BYP will overtake the provided value to VCO_BYP without protection Note Read i...

Page 107: ...s bit is cleared by hardware when PLL switches to freerunning mode When the bit value changes from 0 to 1 bit OSCDISC 0 0B Normal or freerunning operation default 1B PrescalerMode VCOisbypassed PLLout...

Page 108: ...k input is lower as expected 3 On loss of lock detection LOCK 1 0 and when VCOBYP 0 PLL switches to freerunning mode 4 Loss of lockNMIrequestisactivatedonlyonloss of lock detection when VCOBYP 0 and S...

Page 109: ...written with 0 PDIV 9 8 rwpw PLL PDIV Divider This is a PASSWD protected bit When the protection scheme see Chapter 7 14 is activated default this bit cannot be written directly 00 4 01 5 default 10 6...

Page 110: ...higher than that specified for the device 00B K2 2 01B K2 3 10B K2 4 11B K2 5 CLKREL 3 0 rw Slow Down Clock Divider for fCCLK Generation This setting is effective only when the device is enabled in S...

Page 111: ...ion RES 31 1 r Reserved This bit field is always read as zero PBA0CLKREL 0 rwpw PBA0 Clock Divider This Flag configures the PBA0 clock divider Note This is a PASSWD protected bit When the protection s...

Page 112: ...with 0 SYSCLKSEL 7 6 rw System Clock Select Note This is a PASSWD protected bit When the protection scheme see Chapter 7 14 is activated default this bit cannot be written directly This bit field defi...

Page 113: ...or by which the system clock is divided down with respect to the synchronous NVMACCCLK clock Note Can only be changed via dedicated BROM routine 00B Divide by 1 01B Divide by 2 10B Divide by 3 11B Div...

Page 114: ...0 if read should be written with 0 CLKWDT_IE 8 rwpw Clock Watchdog Interrupt Enable Returns 0 if read should be written with 0 Note This is a PASSWD protected bit When the protection scheme see Chapte...

Page 115: ...the bandgap clock divider Note This is a PASSWD protected bit When the protection scheme see Chapter 7 14 is activated default this bit cannot be written directly 0B divide by 2 1B divide by 1 BGCLK_S...

Page 116: ...The clock should be always at 2 MHz 00000B fsys 00001B fsys 2 00010B fsys 3 00011B fsys 4 00100B fsys 5 00101B fsys 6 00110B fsys 7 00111B fsys 8 01000B fsys 9 01001B fsys 10 01010B fsys 11 01011B fsy...

Page 117: ...E_4 Table 47 Possible Clock Configurations Scenarios1 1 besides of this scenarios which represent a kind of worst case all other scenarios shall not lead to an unrecoverable system state fsys MHz pclk...

Page 118: ...ystem clock is divided for the post processing of ADC1 00B Divide by 1 01B Divide by 2 10B Divide by 3 11B Divide by 4 RES 7 4 r Reserved Returns 0 if read should be written with 0 ADC1_CLK_DIV 3 0 rw...

Page 119: ...ld Bits Type Description RES 31 25 r Reserved Returns 0 if read should be written with 0 PLL_LOCK 24 r PLL LOCK Status This bit field indicates the PLL lock status 0B PLL has not locked 1B PLL has loc...

Page 120: ...the lower limit 11B The TFILT_CLK clock is not inside the specified limit RES 7 2 r Reserved Returns 0 if read should be written with 0 APCLK1STS 1 0 r Analog Peripherals Clock Status This bit field r...

Page 121: ...OCK Status Clear RES 23 17 r Reserved Returns 0 if read should be written with 0 APCLK3SCLR 16 w Analog Peripherals Clock 3 Status Clear This bit field is used for APCLK3 Status Clear RES 15 9 r Reser...

Page 122: ...vided COUTS1 6 rw Clock Out Source Select Bit 1 0B fCCLK is selected 1B Based on setting of COUTS0 TLEN 5 rw Toggle Latch Enable Enable this bit if 50 duty cycle is desired on CLKOUT Thisbitisonlyappl...

Page 123: ...t Divider 0000B fsys 0001B fsys 2 0010B fsys 3 0011B fsys 4 0100B fsys 6 0101B fsys 8 0110B fsys 10 0111B fsys 12 1000B fsys 14 1001B fsys 16 1010B fsys 18 1011B fsys 20 1100B fsys 24 1101B fsys 32 11...

Page 124: ...re the MCU system starts operation with the release of the MCU CPU and NVM resets With all resets except soft and SCU watchdog timer resets the boot configuration is latched The CPU starts to execute...

Page 125: ...t indication bit n except indication bits n except reset indication bit n except reset indication bit n except certainstatus bits1 Peripherals n n n n n Debug System n n n n n Port Control n n n n n F...

Page 126: ...are reset In this case the wake up indicator bit WKRS is also set Wake up reset has the next highest priority after power on brown out reset In user mode the system clock is switched to the PLL output...

Page 127: ...ASSWD protected bit When the protection scheme see Chapter 7 14 is activated default this bit cannot be written directly 0B Lockup is disabled 1B Lockup is enabled RES 6 1 r Reserved Returns 0 if read...

Page 128: ...U DM 7 4 6 Booting Scheme After any power on reset brown out reset hardware reset WDT1 reset or wake up reset the pins TMS P0 0 P0 2 together choose different modes Table 55 shows the boot selection o...

Page 129: ...stem components individually Clock speed reduction of some peripheral components Power down of the entire system with fast restart capability Reducing or removing the power supply to power domains Fig...

Page 130: ...low down frequency The CPU and peripherals are clocked at this lower frequency The Slow Down Mode is terminated by clearing bit SD 7 5 2 2 Stop Mode In the Stop Mode the NVM is put into NVM shutdown m...

Page 131: ...estore modules to operational mode including the oscillator and PLL On stable clock per user configuration is restored peripheral clock gating CPU clock gating is removed and the CPU starts to run fro...

Page 132: ...be woken up be this external event it stays in thread mode and continue to execute the code before it entered stop mode This is the recommended procedure to enter stop mode 7 5 2 3 Sleep Mode In the...

Page 133: ...otected bit When the protection scheme see Chapter 7 14 is activated default this bit cannot be written directly PD 2 rwh1 Power Down Mode Stop mode Enable Active High Setting this bit will cause the...

Page 134: ...range of some milliseconds Alternatively for fast wake up from Power Down mode while avoiding this power consumption the user can selectively enable internal oscillator as clock source and disable OSC...

Page 135: ...peration complete Debug Mode user IRAM event and supply prewarning Some NMI sources can be triggered by one of several events These NMI sources are ORed to generate an NMI interrupt directly to the co...

Page 136: ...IEN within the core may block or transfer these interrupt requests to the core interrupt controller An enabled interrupt request is acknowledged when the core vectors to the interrupt routine The soft...

Page 137: ...rupt receive transmit error UART1 10 UART1 ASC LIN interrupt receive transmit t2 linsync1 LIN UART2 11 UART2 interrupt receive transmit t21 External interrupt EINT2 EXINT0 12 External interrupt EINT0...

Page 138: ...rol Register 1 02CH 0000 0000H SCU_WAKECON Wakeup Interrupt Control Register 078H 0000 0000H Interrupt Registers Interrupt Flag Registers SCU_IRCON0 Interrupt Request Register 0 004H 0000 0000H SCU_IR...

Page 139: ...ters Register IEN0 contains the global interrupt masking bit EA which can be cleared to block all pending interrupt requests at once The NMI interrupt vector is shared by a number of sources each of w...

Page 140: ...Description EA 31 rw Global Interrupt Mask 0B All pending interrupt requests except NMI are blocked from the core 1B Pending interrupt requests are not blocked from the core RES 30 24 r Reserved Retu...

Page 141: ...if read should be written with 0 VTOR_BYP 1 0 rw Vector Table Bypass Mode 00B VTOR is not remapped ROM Start Address 0x0000000000 01B VTOR is remapped to RAM Start Address 0x1800000000 10B VTOR is re...

Page 142: ...ed 1B NVM Map Error NMI is enabled NMIOWD 4 rw Oscillator Watchdog NMI Enable 0B Oscillator watchdog NMI is disabled 1B Oscillator watchdog NMI is enabled NMIOT 3 rw NMI OT Enable 0B NMI OT is disable...

Page 143: ...e external interrupt 2 may be disabled individually and is disabled by default after reset Note Several external interrupts support alternative input pin selected via MODPISEL register in the SCU When...

Page 144: ...er 1 02CH see Table 65 Field Bits Type Description RES 31 10 r Reserved Returns 0 if read should be written with 0 MON5 9 8 rw MON5 Input Trigger Select 00B external interrupt MON is disabled 01B Inte...

Page 145: ...0B Interrupt on falling edge 11B Interrupt on both rising and falling edge Table 65 RESET of SCU_EXICON1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000H RESET...

Page 146: ...rns 0 if read should be written with 0 EXINT2F 5 r Interrupt Flag for External Interrupt 2x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt on falling edge...

Page 147: ...red Table 67 RESET of SCU_IRCON0 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000H RESET_TYPE_3 SCU_IRCON0CLR Offset Reset Value Interrupt Request 0 Clear Regis...

Page 148: ...pt 0x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared EXINT0RC 0 w Interrupt Flag for External Interrupt...

Page 149: ...ot occurred 1B Interrupt on rising edge event has occurred MON3F 5 r Interrupt Flag for MON3x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt on falling ed...

Page 150: ...Field Bits Type Description RES 31 10 r Reserved Returns 0 if read should be written with 0 MON5FC 9 w Interrupt Flag for MON5x on falling edge This bit is set by hardware and can only be cleared by...

Page 151: ...cleared MON2FC 3 w Interrupt Flag for MON2x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared MON2RC 2 w...

Page 152: ...t is set by hardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred TIR1 1 r Transmit Interrupt Flag for SSC1 This bit is set by hardware and c...

Page 153: ...This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared TIR1C 1 w Transmit Interrupt Flag for SSC1 This bit is set by hardware...

Page 154: ...t is set by hardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred TIR2 1 r Transmit Interrupt Flag for SSC2 This bit is set by hardware and c...

Page 155: ...This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared TIR2C 1 w Transmit Interrupt Flag for SSC2 This bit is set by hardware...

Page 156: ...hould be written with 0 CCU6SR2 16 r Interrupt Flag 2 for CCU6 This bit is set by hardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred RES 1...

Page 157: ...icrocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 75 RESET of SCU_IRCON4 Register Reset Type Reset Values Reset Short Name Reset M...

Page 158: ...if read should be written with 0 CCU6SR2C 16 w Interrupt Flag 2 for CCU6 This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared...

Page 159: ...crocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 76 RESET of SCU_IRCON4CLR Register Reset Type Reset Values Reset Short Name Reset...

Page 160: ...07CH see Table 77 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 WAKEUP 0 r Interrupt Flag for Wakeup This bit is set by hardware and can only be cleared b...

Page 161: ...ster 19CH see Table 78 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 WAKEUPC 0 w Clear Flag for Wakeup Interrupt This bit is set by hardware and can only b...

Page 162: ...t Status Timer 6 of GPT Module Interrupt Status 0B No Timer 6 Interrupt has occurred 1B Timer 6 Interrupt has occurred GPT2T5 3 r GPT Module 2 Timer5 Interrupt Status Timer 5 of GPT2 Module Interrupt...

Page 163: ...crocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 79 RESET of SCU_GPT12IRC Register Reset Type Reset Values Reset Short Name Reset...

Page 164: ...6 Interrupt Status Timer 6 of GPT Module Interrupt Status 0B Interrupt event is not cleared 1B Interrupt event is cleared GPT2T5C 3 w GPT Module 2 Timer5 Interrupt Status Timer 5 of GPT2 Module Interr...

Page 165: ...crocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 80 RESET of SCU_GPT12ICLR Register Reset Type Reset Values Reset Short Name Reset...

Page 166: ...ISUP 7 r Supply Prewarning NMI Flag This flag is cleared automatically by hardware when the corresponding event flags are cleared 0B No supply prewarning NMI has occurred 1B Supply prewarning has occu...

Page 167: ...1B OT NMI event has occurred FNMINVM 2 r NVM Operation Complete NMI Flag This bit is set by hardware and can only be cleared by software 0B No NVM NMI has occurred 1B NVM operation complete event has...

Page 168: ...red when the sources are cleared 0B Interrupt event is not cleared 1B Interrupt event is cleared FNMIECCC 6 w ECC Error NMI Flag This flag is cleared automatically by hardware when the corresponding e...

Page 169: ...t is not cleared 1B Interrupt event is cleared FNMINVMC 2 w NVM Operation Complete NMI Flag This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interru...

Page 170: ...rupt is disabled 1B Receive interrupt is enabled TIREN2 9 rw SSC 2 Transmit Interrupt Enable 0B Transmit interrupt is disabled 1B Transmit interrupt is enabled EIREN2 8 rw SSC 2 Error Interrupt Enable...

Page 171: ...icrocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 83 RESET of SCU_MODIEN1 Register Reset Type Reset Values Reset Short Name Reset...

Page 172: ...e Interrupt Enable 0B Receive interrupt is disabled 1B Receive interrupt is enabled EXINT2_EN 5 rw External Interrupt 2 Enable 0B External interrupt is disabled 1B External interrupt is enabled RES 4...

Page 173: ...U_MODIEN3 Offset Reset Value Peripheral Interrupt Enable Register 3 038H see Table 85 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 IE0 0 rw External Inter...

Page 174: ...U_MODIEN4 Offset Reset Value Peripheral Interrupt Enable Register 4 03CH see Table 86 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 IE1 0 rw External Inter...

Page 175: ...0 if read should be written with 0 MON5IE 4 rw MON5 Interrupt Enable 0B disabled 1B enabled MON4IE 3 rw MON4 Interrupt Enable 0B disabled 1B enabled MON3IE 2 rw MON3 Interrupt Enable 0B disabled 1B en...

Page 176: ...and Reload Interrupt Enable 0B Interrupt is disabled 1B Interrupt is enabled T6IE 4 rw GPT12 T6 Interrupt Enable 0B Interrupt is disabled 1B Interrupt is enabled T5IE 3 rw GPT12 T5 Interrupt Enable 0...

Page 177: ...ly this includes all the flags of NMISR register FNMIPLL FNMINVM FNMIOCDS FNMIOWD FNMIMAP and indirectly FNMIECC and FNMISUP In the case of watchdog resets the requestor can be identified via the rese...

Page 178: ...ine also enables the corresponding TXD line Peripheral Input Select Register SCU_MODPISEL Offset Reset Value Peripheral Input Select Register 0B8H see Table 89 Field Bits Type Description RES 31 19 r...

Page 179: ...rrupt 2 Input Select 00B External Interrupt Input EXINT2_0 is selected 01B External Interrupt Input EXINT2_1 is selected 10B External Interrupt Input EXINT2_2 is selected 11B External Interrupt Input...

Page 180: ...om CCU6 Output cc6_ch0 T2EXCON 6 rw Timer 2 External Input Control 0B Timer 2 Input T2EX is selected by bit field SCU_MODPISEL2 T2EXIS 1B Timer 2 Input T2EX is connected to signal from CCU6 Output cc6...

Page 181: ...LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 90 RESET of SCU_MODPISEL1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TY...

Page 182: ...T21EX_1 is selected 10B Timer 21 Input T21EX_2 is selected 11B Timer 21 Input T21EX_3 is selected T2EXIS 5 4 rw Timer 2 External Input Select Note This selection takes effect only when SCU_MODPISEL1 T...

Page 183: ...crocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 91 RESET of SCU_MODPISEL2 Register Reset Type Reset Values Reset Short Name Reset...

Page 184: ...urns 0 if read should be written with 0 URIOS2 6 rw UART2 Input Output Select Note To select TXD2_1 as the Transmitter output the Port ALTSELx registers need to be configured additionally 0B UART2 Rec...

Page 185: ...Driver Strength1 and Edge Shape2 000B Strong driver and sharp edge mode 001B Strong driver and medium edge mode 010B Strong driver and soft edge mode 011B Weak driver 100B Medium driver 101B Medium d...

Page 186: ...000B Strong driver and sharp edge mode 001B Strong driver and medium edge mode 010B Strong driver and soft edge mode 011B Weak driver 100B Medium driver 101B Medium driver 110B Medium driver 111B Weak...

Page 187: ...e respective driver can deliver to the external circuitry 2 Defines the switching characteristics to the respective new output driver This also influences the peak currents through the driver when pro...

Page 188: ...rong driver and sharp edge mode 001B Strong driver and medium edge mode 010B Strong driver and soft edge mode 011B Weak driver 100B Medium driver 101B Medium driver 110B Medium driver 111B Weak driver...

Page 189: ...2 0 rw P1 0 Port Driver Mode Code Driver Strength1 and Edge Shape2 000B Medium driver 001B Not used 010B Not used 011B Weak driver 100B Medium driver 101B Medium driver 110B Medium driver 111B Weak dr...

Page 190: ...te in the weak and medium driver modes SCU_TCCR Offset Reset Value Temperature Compensation Control Register 0F4H see Table 95 Field Bits Type Description RES 31 2 r Reserved Returns 0 if read should...

Page 191: ...1 6 r Reserved Returns 0 if read should be written with 0 GPT12_SEL 5 rw CCU6 Trigger Configuration 0B CCU6_INT is triggered by Timer21 1B CCU6_INT is triggered by GPT12PISEL GPT12 TRIG_CONF 4 rw CCU6...

Page 192: ...al the Timer 13 of CCU6 is used Figure 36 Differential Unit 7 8 1 Differential Unit Trigger 7 8 1 1 Differential Unit Trigger register Peripheral Input Select Register 4 Table 96 RESET of SCU_GPT12PIS...

Page 193: ...selected RES 23 19 r Reserved Returns 0 if read should be written with 0 DU3TRIGGEN 18 16 rw Differential Unit Trigger Enable Note These bits configure the enable input of the differential unit 000B...

Page 194: ...erential Unit Trigger Enable Note These bits configure the enable input of the differential unit 000B CC60 is selected 001B CC61 is selected 010B CC62 is selected 011B COUT60 is selected 100B COUT61 i...

Page 195: ...ational status of each individual digital peripheral Peripherals which are not required for a particular functionality can be disabled by programming the assigned register bits which would gate off th...

Page 196: ...w SSC2 Disable Request Active high 0B SSC is in normal operation default 1B Request to disable the SSC RES 7 5 r Reserved Returns 0 if read should be written with 0 GPT12_DIS 4 rw General Purpose Time...

Page 197: ...System Control Unit Digital Modules SCU DM ADC1_DIS 0 rw ADC1 Disable Request Active high 0B ADC1 is in normal operation default 1B Request to disable the ADC Table 98 RESET of SCU_PMCON Register Rese...

Page 198: ...Type Description RES 31 11 r Reserved Returns 0 if read should be written with 0 ADC1_SUSP 10 rw ADC1 Unit Debug Suspend Bit 0B ADC1 will not be suspended 1B ADC1 will be suspended MU_SUSP 9 rw Measur...

Page 199: ...3 in Capture Compare Unit will not be suspended 1B Timer 13 in Capture Compare Unit will be suspended T12SUSP 1 rw Timer 12 Debug Suspend Bit When suspended additionally the T12 PWM outputs are set to...

Page 200: ...rator Control and Status Registers Baud Rate Control Register 1 SCU_BCON1 Offset Reset Value Baud Rate Control Register 1 088H see Table 100 Field Bits Type Description RES 31 4 r Reserved Returns 0 i...

Page 201: ...icrocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 100 RESET of SCU_BCON1 Register Reset Type Reset Values Reset Short Name Reset M...

Page 202: ...rate timer with the reload and fractional divider values from the BG register the first instruction cycle after BCON R is set SCU_BCON2 Offset Reset Value Baud Rate Control Register 2 098H see Table 1...

Page 203: ...r Low Byte 1 08CH see Table 102 Field Bits Type Description RES 31 5 r Reserved Returns 0 if read should be written with 0 BG1_FD_SEL 4 0 rw Fractional Divider Selection Selects the fractional divider...

Page 204: ...n RES 31 5 r Reserved Returns 0 if read should be written with 0 BG2_FD_SEL 4 0 rw Fractional Divider Selection Selects the fractional divider to be n 32 where n is the value of FD_SEL and is in the r...

Page 205: ...should be written with 0 BG1_BR_VALUE 10 0 rw Baud Rate Timer Reload Value UART1 11 bit Baud Rate Timer Reload value Note If the baud rate generation is running this register shows the actual timer v...

Page 206: ...should be written with 0 BG2_BR_VALUE 10 0 rw Baud Rate Timer Reload Value UART2 11 bit Baud Rate Timer Reload value Note If the baud rate generation is running this register shows the actual timer v...

Page 207: ...Figure 37 Structure of Baudrate Generator 7 12 1 LIN Break and Sync Byte Detection Control 7 12 1 1 LIN Break and Sync Byte Registers LIN Status Register SCU_LINST Offset Reset Value LIN Status Regist...

Page 208: ...be cleared by software 0B End of SYN Byte is not detected 1B End of SYN Byte is detected BRK 3 r Break Field Flag This bit is set by hardware and can only be cleared by software 0B Break Field is not...

Page 209: ...5 w SYN Byte Error Interrupt Flag This bit is set by software and can only be cleared by hardware 0B Error in SYN Byte not cleared 1B Error in SYN Byte cleared EOFSYNC 4 w End of SYN Byte Interrupt F...

Page 210: ...RES 31 3 r Reserved Returns 0 if read should be written with 0 NVMIE 2 rw NVM Double Bit ECC Error Interrupt Enable 0B No NMI is generated when a double bit ECC error occurs reading NVM 1B An NMI is g...

Page 211: ...ith 0 RES 5 r Reserved Returns 0 if read should be written with 0 RSBE 4 r RAM Single Bit Error This bit is set by hardware and can be cleared only by software 0B No single bit error on RAM has occurr...

Page 212: ...written with 0 RSBEC 4 w RAM Single Bit Error Clear This bit is set by software and can be cleared only by hardware 0B A single bit error on RAM is not cleared 1B A single bit error on RAM is cleared...

Page 213: ...crocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 110 RESET of SCU_EDCSCLR Register Reset Type Reset Values Reset Short Name Reset...

Page 214: ...2 CCLK cycles there will be a recount of 32 CCLK cycles Note It is recommended to disable interrupts before writing to this register otherwise interrupts might delay the write access the protected bit...

Page 215: ...s reset by reset_type_4 PW_MODE 1 0 rw Bit Protection Scheme Control Bit These two bits cannot be written directly To change the value between 11B and 00B the bit field PASS must be written with 11000...

Page 216: ...V was successful checksum was correct 1 nok initialisation of trimming parameter from NMV was not successful checksum was not correct As a backup default values form Boot ROM are used Note this bit is...

Page 217: ...and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 113 RESET of SCU_SYS_STRTUP_STS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET...

Page 218: ...tected 1B CBSL Region Password is installed CBSL region is protected LIN_PW 12 r Status of Linear Region Password Protection 0B Linear Region Password is not installed Linear region is not protected 1...

Page 219: ...VM Read Protection of Data in Linear Sectors 0B The data in sectors of the linearly mapped area can not be read 1B The data in sectors of the linearly mapped area can be read EN_RD_NL 3 r NVM Read Pro...

Page 220: ...ocontroller with LIN and Power Switches for Automotive Applications System Control Unit Digital Modules SCU DM Table 114 RESET of SCU_NVM_PROT_STS Register Reset Type Reset Values Reset Short Name Res...

Page 221: ...ROM_PROT_ERR 4 rh ROM Access Protection 0B No Protection error 1B Protection error NVM_SFR_ADDR_ERR 3 rh NVM SFR Address Protection 0B No Protection error 1B Protection error NVM_SFR_PROT_ERR 2 rh NVM...

Page 222: ...g SCU_ID Offset Reset Value Identity Register 0A8H see Table 116 Field Bits Type Description RES 31 8 r Reserved Returns 0 if read should be written with 0 PRODID 7 3 r Product ID 10000B VERID 2 0 r V...

Page 223: ...ould be written with 0 SASTATUS 7 6 rw Service Algorithm Status 00B Depending on SECTORINFO there are two possible outcomes For SECTORINFO 00H NVM initialization issuccessfulandnoSAisexecuted ForSECTO...

Page 224: ...e Description RES 31 2 r Reserved Returns 0 if read should be written with 0 EMPROP 1 rw Emergency Program Operation Status Bit This bit is used to monitor the status of the emergency program operatio...

Page 225: ...vice enters and exits Sleep and Stop Mode External Watchdog WDT1 independent system watchdog to monitor system activity 8 2 Introduction 8 2 1 Block Diagram The System Control Unit of the power module...

Page 226: ...s Those are MI_CLK and TFILT_CLK are out of Range MI Clock settings for fsys MI_CLK and TFILT_CLK Clock settings are out of required range and as a result the analog functionalities cannot be guarante...

Page 227: ...ation stay on mi_clk but reconfigure PLL to re gain the required clock frequency This would be the most time consuming measure to avoid emergency shutdown of the above listed modules switch to divider...

Page 228: ...00H 50006FFFH SCU_PM Table 120 Register Overview Register Short Name Register Long Name Offset Address Reset Value Clock Generation Unit Register SCUPM_AMCLK_FREQ_STS Analog Module Clock Frequency Sta...

Page 229: ...UPM_AMCLK_FREQ_STS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_4 00000000H RESET_TYPE_4 SCUPM_AMCLK_CTRL Offset Reset Value Analog Module Clock Control Register 04H se...

Page 230: ...1_LOW_HYS 15 14 rw Analog Module Clock 1 MI_CLK Lower Hysteresis AMCLK1_LOW_TH 13 8 rw Analog Module Clock 1 MI_CLK Lower Limit Threshold 0 75 Mhz AMCLK1_LOW_TH AMCLK1_UP_HYS 7 6 rw Analog Module Cloc...

Page 231: ...itored by the Measurement Unit and 10 Bit ADC The supply voltages VS VBAT_SENSE VDDP and VDDC are monitored by the Measurement Unit and the 10 Bit ADC module The Measurement Unit can be considered as...

Page 232: ...ge triggered attribute rwhe Therefore each IRQ_STS register has also an STS register where the current supply status can be monitored prewarn_sup_nmi VBAT_SENSE_UV_IS VBAT_SENSE_OV_IS 1 0 0 0 MI Volta...

Page 233: ...detection for all system relevant supplies These Interrupts are edge triggered Interrupts SCUPM_SYS_IS Interrupts for Analog Modules Table 125 Register Overview Register Short Name Register Long Name...

Page 234: ...CTIVE no status set 1B ACTIVE at least one status set RES 23 r Reserved Always read as 0 LIN_FAIL_STS 22 r LIN Fail Status Note This flag is the LIN_OT_STS 0B INACTIVE no status set 1B ACTIVE at least...

Page 235: ...0B INACTIVE no status set 1B ACTIVE at least one status set RES 15 13 r Reserved Always read as 0 RES 12 r Reserved REFBG_UPTHWARN_ IS 11 rwhxr 8 Bit ADC2 Reference Overvoltage ADC2 Channel 3 interrup...

Page 236: ..._IS 2 r High Side Driver 1 Fail Interrupt Status Note This flag is an OR combination of HS1_OC_IS HS1_OT_IS and HS1_OL_IS 0B INACTIVE no status set 1B ACTIVE at least one status set LS2_FAIL_IS 1 r Lo...

Page 237: ...e occurred VBAT_OV_STS 21 rwhxr VBAT Overvoltage Status 0B No Overvoltage occurred 1B Overvoltage occurred VDDEXT_UV_STS 20 rwhxr VDDEXT Undervoltage Status 0B No Undervoltage occurred 1B Undervoltage...

Page 238: ...rvoltage Interrupt occurred VBAT_OV_IS 5 rwhxre VBAT Overvoltage Interrupt Status 0B No Overvoltage Interrupt occurred 1B Overvoltage Interrupt occurred VDDEXT_UV_IS 4 rwhxre VDDEXT Undervoltage Inter...

Page 239: ...alue System Interrupt Status Clear Register 14H see Table 128 Field Bits Type Description RES 31 26 r Reserved Always read as 0 SYS_OT_SC 25 w System Overtemperature Shutdown status clear 0B No Clear...

Page 240: ...Switches for Automotive Applications System Control Unit Power Modules SCU PM RES 7 0 r Reserved Always read as 0 Table 128 RESET of SCUPM_SYS_ISCLR Register Reset Type Reset Values Reset Short Name...

Page 241: ...No Clear 1B Clear VS_OV_SC 22 w VS Overvoltage Status clear 0B No Clear 1B Clear VBAT_OV_SC 21 w VBAT Overvoltage Status clear 0B No Clear 1B Clear VDDEXT_UV_SC 20 w VDDEXT Undervoltage Status clear 0...

Page 242: ...SC 6 w VS Overvoltage Interrupt Status clear 0B No Clear 1B Clear VBAT_OV_ISC 5 w VBAT Overvoltage Interrupt Status clear 0B No Clear 1B Clear VDDEXT_UV_ISC 4 w VDDEXT Undervoltage Interrupt Status cl...

Page 243: ...t Control Register 28H see Table 130 Field Bits Type Description RES 31 12 r Reserved Always read as 0 REFBG_UPTHWARN_ IE 11 rw Reference Voltage Overvoltage Interrupt Enable 0B Interrupt is disabled...

Page 244: ...nterrupt is disabled 1B Interrupt is enabled VS_OV_IE 6 rw VS Overvoltage Interrupt Enable 0B Interrupt is disabled 1B Interrupt is enabled VBAT_OV_IE 5 rw VBAT Overvoltage Interrupt Enable 0B Interru...

Page 245: ...t Unit and the modules which are evaluated by the Unit The following modules are controlled by this statemachine Analog Modules controlled by Power Control Unit Central Reference Voltage Generation Ce...

Page 246: ...s like load jumps on the supplies The power control unit also handles system failures indicated by the analog measurement interface They are System failures handled by SCU_PM automatic shutdown of pow...

Page 247: ...would require to shutdown all modules which have big contribution to power dissipation e g Low Sides High Sides This procedure has to be implemented in user software Another possibility is to use the...

Page 248: ...fset Address Reset Value Power Control Unit Register SCUPM_PCU_CTRL_STS Power Control Unit Control Status Register 30H 0EE37EF3H SCUPM_PKGCFG1 Package Configuration Register 1 90H 00000100H SCUPM_PCU_...

Page 249: ...of VS Undervoltage disabled RES 7 6 r Reserved Always read as 0 RES 5 r Reserved Always read as 0 RES 4 2 r Reserved Always read as 0 CLKWDT_SD_DIS 1 rw Power Modules Clock Watchdog Shutdown Disable 0...

Page 250: ...ecture v6 M Style ARMv6 unaligned accesses Systick typ 1ms Nested Vectored Interrupt Controller NVIC closely integrated with the processor core to achieve low latency interrupt processing External int...

Page 251: ...processor implements the Thumb 2 instruction set architecture With the optimized feature set the Cortex M0 delivers 32 bit performance in an application space that is usually associated with 8 and 16...

Page 252: ...and SP_main Link register LR R14 Program counter PC R15 Special purpose registers Figure 43 Processor Register Set 9 3 1 1 General Purpose Registers The general purpose registers R0 R12 are 32 bit reg...

Page 253: ...LIN and Power Switches for Automotive Applications Arm Cortex M0 Core Program Status Register Register PSR is the Program Status Register Interrupt MaskRegister Register PRIMASK is the Interrupt Mask...

Page 254: ...Register 018H 00XXXXXXH CPU_SYSTICK_CALIB SysTick Calibration Value Register 01CH X0XXXXXXH CPU_NVIC_ISER Interrupt Set Enable 100H 00000000H CPU_NVIC_ICER Interrupt Clear Enable 180H 00000000H CPU_NV...

Page 255: ...URCE 2 rw CLK Source Selects the SysTick timer clock source 0B external reference clock 1B processor clock TICKINT 1 rw TICKINT Enables SysTick exception request 0B counting down to 0 does not assert...

Page 256: ...RELOAD value of N 1 For example if the SysTick interrupt is required every 100 clock pulses set RELOAD to 99 SysTick Current Value Registers Field Bits Type Description RES 31 24 r Reserved RELOAD 23...

Page 257: ...SET_TYPE_3 CPU_SYSTICK_CALIB Offset Reset Value SysTick Calibration Value Register 01CH see Table 139 Field Bits Type Description NOREF 31 r No Reference Clock Indicates that no separate reference clo...

Page 258: ...terrupt Int_DU 21 rw Interrupt Set for Differential Unit 0B DISABLED no effect on write 1B ENABLE enables the associated interrupt Int_HS2 20 rw Interrupt Set for HS2 0B DISABLED no effect on write 1B...

Page 259: ...ART1 0B DISABLED no effect on write 1B ENABLE enables the associated interrupt Int_SSC2 9 rw Interrupt Set for SSC2 0B DISABLED no effect on write 1B ENABLE enables the associated interrupt Int_SSC1 8...

Page 260: ...ar for PORT2 0B DISABLE on reads the associated interrupt is disabled no effect on write 1B ENABLE on reads the associated interrupt is enabled on writes the associated interrupt is disabled Int_MON 2...

Page 261: ...on write 1B ENABLE on reads the associated interrupt is enabled on writes the associated interrupt is disabled Int_LS1 17 rw Interrupt Clear for LS1 0B DISABLE on reads the associated interrupt is dis...

Page 262: ...e associated interrupt is disabled Int_CCU6SR3 7 rw Interrupt Clear for CCU6 SR3 0B DISABLE on reads the associated interrupt is disabled no effect on write 1B ENABLE on reads the associated interrupt...

Page 263: ...ites the associated interrupt is disabled Table 141 RESET of CPU_NVIC_ICER Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 CPU_NVIC_ISPR Offset Re...

Page 264: ...s the associated interrupt is not pending no effect on writes 1B Pending the associated interrupt is pending Int_LS1 17 rw Interrupt Set Pending for LS1 0B Not Pending on reads the associated interrup...

Page 265: ...o effect on writes 1B Pending the associated interrupt is pending Int_CCU6SR1 5 rw Interrupt Set Pending for CCU6 SR1 0B Not Pending on reads the associated interrupt is not pending no effect on write...

Page 266: ...pt is pending on writes the status of the associated interrupt is changed to not pending Int_DU 21 rw Interrupt Clear Pending for Differential Unit 0B Not Pending on reads the associated interrupt is...

Page 267: ...rrupt is not pending no effect on writes 1B Pending on reads the associated interrupt is pending on writes the status of the associated interrupt is changed to not pending Int_EXINT1 13 rw Interrupt C...

Page 268: ...hanged to not pending Int_CCU6SR1 5 rw Interrupt Clear Pending for CCU6 SR1 0B Not Pending on reads the associated interrupt is not pending no effect on writes 1B Pending on reads the associated inter...

Page 269: ...t Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 CPU_NVIC_IPR0 Offset Reset Value Interrupt Priority 400H see Table 144 Field Bits Type Description PRI_ADC1 31 30 rw Prior...

Page 270: ...29 24 r Reserved PRI_CCU6SR2 23 22 rw Priority for CCU6 SR2 RES 21 16 r Reserved PRI_CCU6SR1 15 14 rw Priority for CCU6 SR1 RES 13 8 r Reserved PRI_CCU6SR0 7 6 rw Priority for CCU6 SR0 RES 5 0 r Rese...

Page 271: ...ority for CCU6 SSC2 RES 13 8 r Reserved PRI_SSC1 7 6 rw Priority for CCU6 SSC1 RES 5 0 r Reserved Table 146 RESET of CPU_NVIC_IPR2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RES...

Page 272: ...ority for External Int 0 RES 5 0 r Reserved Table 147 RESET of CPU_NVIC_IPR3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 CPU_NVIC_IPR4 Offset...

Page 273: ...ble 149 Field Bits Type Description PRI_PORT2 31 30 rw Priority for PORT2 RES 29 24 r Reserved PRI_MON 23 22 rw Priority for MON RES 21 16 r Reserved PRI_DU 15 14 rw Priority for Differential Unit RES...

Page 274: ...H PARTNO 15 4 r Part Number Implementation defined REVISION 3 0 r Revision Number Implementation defined Table 150 RESET of CPU_CPUID Register Reset Type Reset Values Reset Short Name Reset Mode Note...

Page 275: ...On writes sets the PendSV exception as pending On reads indicates the current state of the exception Note Writing 1 to this bit is the only way to set the PENDSV exception state to pending 0B on write...

Page 276: ...ontains the active exception number Nonzero is the exception number1 of the currently active exception Note Subtract 16 from this value to obtain the CMSISIRQ number that identifies the corresponding...

Page 277: ...d SYSRESETRE Q 2 w System Reset Request This bit reads as 0B 0B no effect 1B request a system level reset VECTCLRACTI VE 1 w VECTCLRACTIVE Reserved for debug use This bit reads as 0B Note When writing...

Page 278: ...enabled events and all interrupts including disabled interrupts can wake up the processor RES 3 r Reserved SLEEPDEEP 2 rw Sleep Deep Controls whether the processor uses sleep or deep sleep as its low...

Page 279: ...n exception entry the processor uses bit 9 of the stacked PSR to indicate the stack alignment On return from the exception it uses this stacked bit to restore the correct stack alignment RES 8 4 r Res...

Page 280: ...SET of CPU_SHPR2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 CPU_SHPR3 Offset Reset Value System Handler Priority Register 3 D20H see Table 15...

Page 281: ...8 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Arm Cortex M0 Core Table 156 RESET of CPU_SHPR3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 282: ...barrier operation N for the number of registers in the register list to be loaded or stored including PC or LR W for the number of cycles spent waiting for an appropriate event Table 157 Instruction S...

Page 283: ...rom stack POP reglist 1 N Branch Conditional B cc label 1 or 1 P2 Unconditional B label 1 P With link BL label 1 P Indirect BX Rm 1 P Indirect with link BLX Rm 1 P State change Supervisor call SVC imm...

Page 284: ...rriers Instruction synchronization ISB 1 B Data memory DMB 1 B Data synchronization DSB 1 B 1 Neighboring load and store single instructions can pipeline their address and data phases This enables the...

Page 285: ...TLE984xQX manipulates operands in the following memory spaces Up to 64 KByte of Flash memory product variant dependant in code space 24 KB Boot ROM memory in code space used for boot code and IP stor...

Page 286: ...tation standard AHB Lite interfaceand Error Correction Code ECC logic if needed MemoryMapARM0_4x vsd Boot ROM 24K Flash up to 64K reserved SRAM up to 4K reserved PBA0 PBA1 reserved Private Peripheral...

Page 287: ...FFF Reserved Reserved 1100_0000 1100_FFFF Code Data Flash up to 64 KBytes1 1 Product variant dependant 1101_0000 17FF_FFFF Reserved Reserved 1800_0000 1800_0FFF Code Data SRAM up to 4 KBytes1 1800_100...

Page 288: ...ved 40014000H 4001BFFFH LS 4001C000H 4001FFFFH Reserved 40020000H 40023FFFH HS 40024000H 40027FFFH Reserved 40028000H 47FFFFFFH Peripherals 1 Reserved 48000000H 48003FFFH T2 48004000H 48004FFFH T21 48...

Page 289: ...NVM Configuration with Special Function Registers through AHB Lite Interface Hardware Memory Protection Logic 11 2 Introduction 11 2 1 Block Diagram The Memory Control Unit is divided in the followin...

Page 290: ...matrix block decodes the access requests coming from the masters and forwards them to the target module interface together with the required sideband signals The AMBA bus matrix block provides all the...

Page 291: ...s basically of three parts used for Startup and boot SW Boot Strap Loader routines User routines 11 4 1 BootROM Addressing The BootROM as visible from the memory map is mapped starting at the address...

Page 292: ...in TLE984xQX has a capacity of 4 Kbyte organized with words of 32 bits The module support 1 bit Error correction and 2 bits error detection per 32 bit word actually requiring 7 bits parity per word Wh...

Page 293: ...ctions executed from an unsafe memory address e g RAM that target the BootROM or NVM are blocked when the respective protection mode is enabled The hardware protection scheme is further described in S...

Page 294: ...ped NVM region itself non linearly mapped NVM region or RAM Data reading instructions executed from the non linearly mapped NVM region targeting RAM Data reading instructions executed from the targeti...

Page 295: ...ction enable disable are described in the Chapter 11 6 2 2 4 Application hint regarding read protection The customer BSL region can also be used as normal user code area In that case special care must...

Page 296: ...instructions executed from the BootROM can target itself Data reading instructions executed from the Customer BSL NVM region can target itself Linear NVM Non Linear NVM or RAM 11 6 2 2 2 NVM Linear P...

Page 297: ...ding accesses triggered by debugger targeting the NVM Linear region Figure 50 shows all the data reading instructions authorized when the BootROM the Customer BSL region and NVM Linear read protection...

Page 298: ...dule to prevent the NVM state machine from accepting any program or erase command including fast invalidation This prevents inadvertent destruction of stored data while protection is set When NVM Non...

Page 299: ...lete code has been programmed into the Customer BSL and Linear NVM regions the protection scheme can be enabled by calling the BootROM password routine by means of the dedicated TLE984xQX BSL mode The...

Page 300: ...target bits are not changed and the content of all the 3 password controlled memory region Customer BSL Linear NVM and Non Linear NVM together with the related passwords is erased to avoid hacking of...

Page 301: ...ction mechanism provided by hardware effective In fact the feature for code download could be used for hacking even if the read protection is set on a region but not the write protection It would then...

Page 302: ...e memory content via debugger is blocked when accessing a read protected region it is still possible to use the other debugger features e g step through breakpoints watchpoints code profiling to perfo...

Page 303: ...rogram and BSL Security option to protect read out via debug interface in application run mode NVM protection mode available which can be enabled disabled with password Write erase access to 100TP e g...

Page 304: ...User Manual 304 Rev 1 1 2019 03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications NVM Module Flash Memory...

Page 305: ...bly The retention time is a statistical figure that depends on the operating conditions of the flash array temperature profile and the accesses to the flash array With an increasing number of program...

Page 306: ...ects 64 bits when a byte is written to the assembly buffer automatically an NVM internal read of the complete block is triggered the byte and the ECC are updated and the complete block is written back...

Page 307: ...eading form the memory array writing to the assembly buffer enabling tearing safe programming of a single page provide basic in module functionality for code protection The main features are listed fo...

Page 308: ...block stores the mapping information of the page in the sector All blocks of a page are ECC protected A page is the smallest granularity of data that can be changed erased or written within the cell...

Page 309: ...ddresses for each mapped sector It is completely handled by the NVM programming related BootROM routines FSM and SFR block This block contains the special function registers SFRs of the NVM module Bes...

Page 310: ...xisting content of a page to the assembly buffer allows the user to modify the content of the assembly buffer and afterwards executes the programming of the data to the memory field followed by a veri...

Page 311: ...number of sectors can be configured not to use the map RAM mapping mechanism i e for these sectors logical and physical page addresses are identical The range of these linearly mapped sectors always s...

Page 312: ...ts are concentrated in one sector and other sectors have only a low number of hot spots a hot spot distribution over several sectors is advisable This hot spot distribution is not supported in HW but...

Page 313: ...re that no NVM operation which changes the content of the data flash module program or erase get interrupted at any time Appropriate actions to support this could be the capacitor at the VS input has...

Page 314: ...ed by the following Watchdog Timer warning before overflow MI_CLK Watchdog Timer overflow event PLL loss of lock Flash on operation complete e g erase OT prewarning Oscillator watchdog detection for t...

Page 315: ...for future use LS1 17 Low Side 1 Interrupt LS2 18 Low Side 2 Interrupt HS1 19 High Side 1 Interrupt HS2 20 High Side 2 Interrupt DU 21 Differential Unit DPP1 product variant dependant only TLE9845QX...

Page 316: ...ode 0 and 1 GPT12 Timer Module Figure 57 Interrupt Request Sources 0 and 1 GPT12 1 GPT12IRC 4 GPT2_T6 GPT12IRC 5 GPT12_CR GPT12IEN 5 CRIE INTISR 1 IEN0 31 InterruptRequestsource0 1_N2 vsd GPT12CR GPT1...

Page 317: ...m 13 3 1 2 Interrupt Node 2 Measurement Unit Figure 58 Interrupt Request Sources 2 MU SCU_PM 1 IEN0 31 INTISR 2 InterruptRequestsource2_MU_N vsd SYS_IRQ_CTRL REFBG_UPTHWARN_IE REF1_STS REFBG_UPTHWARN_...

Page 318: ...1 MON1_IEN ADC1_IRQCLR_1 MON2_ISC ADC1_IRQS_1 MON2_IS ADC1_IRQEN_1 MON2_IEN ADC1_IRQCLR_1 MON3_ISC ADC1_IRQS_1 MON3_IS ADC1_IRQEN_1 MON3_IEN ADC1_IRQCLR_1 MON4_ISC ADC1_IRQS_1 MON4_IS ADC1_IRQEN_1 MON...

Page 319: ...ications Interrupt System 13 3 1 4 Interrupt Node 4 5 6 7 CCU6 Figure 60 Interrupt Request Sources 4 5 6 7 CCU6 InterruptRequestsource4_5_6_7_N vsd IEN0 31 CCU6 Node 3 CCU6SRC3 IRCON4 4 INTISR 7 CCU6...

Page 320: ...SSC Figure 61 Interrupt Request Sources 8 and 9 SSC 1 IRCON3 1 SSC_TIR2 IRCON3 2 SSC_RIR2 MODIEN1 10 RIREN2 INTISR 9 IEN0 31 InterruptRequestSource 8 9_N vsd RIN2 TIR2 MODIEN1 9 TIREN2 IRCON3 0 SSC_EI...

Page 321: ...2 Overflow 1 LINST 4 End of Synch Byte LINST 5 Synch Byte Error 1 LINST SYNEN EXF2 T2_T2CON 6 T2EX EDGESEL T2_T2MOD 5 T2_T2CON1 0 UART1 Transmit UART1 Receive INTISR 10 IEN0 31 InterruptRequestsource1...

Page 322: ...e 63 Interrupt Request Source 11 UART2 1 Timer 21 Overflow 1 EXF2 T21T2CON 6 T21EX EDGESEL T21T2MOD 5 T21T2CON1 0 UART2 Transmit UART2 Receive INTISR 11 IEN0 31 InterruptRequestsource11_N vsd T21T2CON...

Page 323: ...Interrupt System 13 3 1 8 Interrupt Node 12 and 13 Interrupt Figure 64 Interrupt Request Sources 12 and 13 External Interrupt INTISR 12 IEN0 31 InterruptRequestsource12 13_N vsd INTISR 13 EINT0 0 IRC...

Page 324: ...OC_IEN IRQS LS1_OT_IS IRQS LS1_OC_IS LS1_OT_STS IRQEN LS1_OT_IEN LS1_OL_STS IRQEN LS1_OL_IEN IRQS LS1_OL_IS 1 IRQS LS1_OT_PR EWARN_IS LS1_OT_PREWARN_STS IRQEN LS1_OT_PREWARN_IEN IRQEN LS2_OC_IEN IRQS...

Page 325: ...rupt Request Sources 19 20 HS1 HS2 High Side 2 High Side 1 IRQEN HS1_OC_IEN IRQS HS1_OT_IS IRQS HS1_OC_IS HS1_OT_STS IRQEN HS1_OT_IEN HS1_OL_STS IRQEN HS1_OL_IEN IRQS HS1_OL_IS 1 IRQEN HS2_OC_IEN IRQS...

Page 326: ...ADC1 Interrupt Control ADC1_IRQCLR_1 DU1UP_ISC ADC1_IRQS_1 DU1UP_IS ADC1_IRQEN_1 DU1UP_IEN ADC1_IRQCLR_1 DU1LO_ISC ADC1_IRQS_1 DU1LO_IS ADC1_IRQEN_1 DU1LO_IEN ADC1_IRQCLR_1 DU2UP_ISC ADC1_IRQS_1 DU2UP...

Page 327: ...LO_STS MON1_LO_STS MON1_UP_STS ADC1_IRQCLR_2 MON1_UP_ISC ADC1_IRQS_2 MON1_UP_IS ADC1_IRQEN_2 MON1_UP_IEN ADC1_IRQCLR_2 MON1_LO_ISC ADC1_IRQS_2 MON1_LO_IS ADC1_IRQEN_2 MON1_LO_IEN ADC1_IRQCLR_2 MON2_UP...

Page 328: ..._2 P2_1_LO_IS ADC1_IRQEN_2 P2_1_LO_IEN ADC1_IRQCLR_2 P2_2_UP_ISC ADC1_IRQS_2 P2_2_UP_IS ADC1_IRQEN_2 P2_2_UP_IEN ADC1_IRQCLR_2 P2_2_LO_ISC ADC1_IRQS_2 P2_2_LO_IS ADC1_IRQEN_2 P2_2_LO_IEN ADC1_IRQCLR_2...

Page 329: ...Lock NMINVM NMICON 2 NVM Operation Complete NMIOWD NMICON 4 Oscillator Watchdog NMIOCDS NMICON 3 FNMIPLL NMISR 1 FNMINVM NMISR 2 FNMIOWD NMISR 4 NMIMAP NMICON 5 NVM Map Error FNMIMAP NMISR 5 NMIECC N...

Page 330: ...PMU_OT_I E Supply NMI PREWARN_SUP VBAT_UV NMI edge set until clearedby software SYS_SUPPLY_IRQ_STS VB AT_UV_IE SYS_SUPPLY_IRQ_CTRL V BAT_UV_IE PREWARN_SUP VS_UV NMI edge set until clearedby software...

Page 331: ...T_FAIL_EN VDDEXT_UNDER VOLT NMI level set until clearedby software PMU_VDDEXT_CTRL VDD EXT_UV_IS PMU_VDDEXT_CTRL VDD EXT_FAIL_EN CLKWDT NMI level SYS_IS CLKWDT_IS SYS_STS CLKWDT_STS AMCLK_CTRL CLKWDT_...

Page 332: ...nterrupt_Control ADC1CH2_STS ADC1_IRC ADC1_IE ADC1_CH2_IE ADC10 CH3 3 level set until clearedby software ADC1_Interrupt_Control ADC1CH3_STS ADC1_IRC ADC1_IE ADC1_CH3_IE ADC10 CH4 3 level set until cle...

Page 333: ...CU01 4 level 2 per_clk cycles CCU6 Node 0 SCU_IRCON4 CCU6SR0 SCU_IEN0 ECCIP0 CCU11 5 level 2 per_clk cycles CCU6 Node 1 SCU_IRCON4 CCU6SR1 SCU_IEN0 ECCIP1 CCU21 6 level 2 per_clk cycles CCU6 Node 2 SC...

Page 334: ...SYS_IRQ_CTRL LIN_OT_IE LIN OC 10 level LIN SYS_IS LIN_OC_IS SYS_IRQ_CTRL LIN_OC_IE TXD_TMOUT 10 LIN SYS_IS LIN_TMOUT_IS SYS_IRQ_CTRL LIN_TMOU T_IE T21EX 10 T21EX T21T2CON EXF2 T21T2CON1 EXF2EN UART2...

Page 335: ...il clearedby software LS2_OT LS_IRQS LS2_OT_STS LS_IRQEN LS2_OT_IEN LS2 18_2 edge set until clearedby software LS2_OL LS_IRQS LS2_OL_STS LS_IRQEN LS2_OL_IEN INTISR 19 20 HS1 HS2 HS1 19_0 level set unt...

Page 336: ...MONIEN MON2IE WAKEUP 22_2 set until clearedby software SCU_EXICON1 MON3 MONIEN MON3IE WAKEUP 22_3 set until clearedby software SCU_EXICON1 MON4 MONIEN MON4IE WAKEUP 22_4 set until clearedby software S...

Page 337: ...acknowledged its pending interrupt request represented by the interrupt status flag may be automatically cleared by hardware the core Figure 71 Interrupt Structure 1 For the TLE984xQX interrupt source...

Page 338: ...NMIPLL SCU_NMICON NVM Operation Complete NMI NMINVM Overtemperature NMI NMIOT Oscillator Watchdog NMI NMIOWD NVM Map Error NMI NMIMAP ECC Error NMI NMIECC Supply Prewarning NMI NMISUP INTISR 0 XXXXH...

Page 339: ...S_LS_IRQ_CTR L INTISR 18 XXXXH LS2_OC LS2_OC_IE HS_LS_IRQ_CTR L LS2_OT LS2_OT_IE HS_LS_IRQ_CTR L LS2_OL LS2_OL_IE HS_LS_IRQ_CTR L INTISR 19 XXXXH HS1_OC HS1_OC_IE HS_1_IEN HS1_OT HS1_OT_IE HS_1_IEN HS...

Page 340: ...EN INTISR 23 Port2 1 P2_1_UP_IEN P2_1_LO_IEN ADC1_IRQEN_2 Port2 2 P2_2_UP_IEN P2_2_LO_IEN ADC1_IRQEN_2 Port2 3 P2_3_UP_IEN P2_3_LO_IEN ADC1_IRQEN_2 Port2 6 P2_6_UP_IEN P2_6_LO_IEN ADC1_IRQEN_2 Port2 7...

Page 341: ...the polling sequence as shown in Table 162 The interrupt priority is configured in the corresponding NVIC control register Table 164 Interrupt Node Table Service Request Node ID Description GPT1 0 GPT...

Page 342: ...m Control Unit SCU or the System Control Unit for the Power Modules SCU_PM Table 165 Register Short name Register Long Name Offset Address Reset Value CPU_NVIC_IPR0 Interrupt Priority 400H 0000 0000H...

Page 343: ...upt Registers Interrupt Flag Registers SCU_SCON1 UART1 Control Status Register xxxH 0000 0000H SCU_SCON2 UART2 Control Status Register xxxH 0000 0000H SCU_IRCON0 Interrupt Request Register 0 004H 0000...

Page 344: ...ICON are cleared to 0 This implies that all interrupt nodes are disabled by default Interrupt Enable Register 0 SCU_IEN0 Offset Reset Value Interrupt Enable Register 0 01CH see Table 169 Field Bits Ty...

Page 345: ...Error NMI is enabled NMIOWD 4 rw Oscillator Watchdog NMI Enable 0B Oscillator watchdog NMI is disabled 1B Oscillator watchdog NMI is enabled NMIOT 3 rw NMI OT Enable 0B NMI OT is disabled 1B NMI OT i...

Page 346: ...errupt 2 may be disabled individually and is disabled by default after reset Note Several external interrupts support alternative input pin selected via MODPISEL register in the SCU When switching inp...

Page 347: ...Table 172 Field Bits Type Description RES 31 10 r Reserved Returns 0 if read should be written with 0 MON5 9 8 rw MON5 Input Trigger Select 00B external interrupt MON is disabled 01B Interrupt on ris...

Page 348: ...falling edge 11B Interrupt on both rising and falling edge Table 172 RESET of SCU_EXICON1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000H RESET_TYPE_3 SCU_WA...

Page 349: ...should be written with 0 EXINT2F 5 r Interrupt Flag for External Interrupt 2x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt on falling edge event has no...

Page 350: ...RESET of SCU_IRCON0 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000 0000H RESET_TYPE_3 SCU_IRCON0CLR Offset Reset Value Interrupt Request 0 Clear Register 178H see...

Page 351: ...ng edge This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared EXINT0RC 0 w Interrupt Flag for External Interrupt 0x on rising...

Page 352: ...B Interrupt on rising edge event has occurred MON3F 5 r Interrupt Flag for MON3x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt on falling edge event has...

Page 353: ...Type Description RES 31 10 r Reserved Returns 0 if read should be written with 0 MON5FC 9 w Interrupt Flag for MON5x on falling edge This bit is set by hardware and can only be cleared by software 0B...

Page 354: ...C 3 w Interrupt Flag for MON2x on falling edge This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared MON2RC 2 w Interrupt Flag...

Page 355: ...ardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred TIR1 1 r Transmit Interrupt Flag for SSC1 This bit is set by hardware and can only be cl...

Page 356: ...set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared TIR1C 1 w Transmit Interrupt Flag for SSC1 This bit is set by hardware and can only...

Page 357: ...ardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred TIR2 1 r Transmit Interrupt Flag for SSC2 This bit is set by hardware and can only be cl...

Page 358: ...set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared TIR2C 1 w Transmit Interrupt Flag for SSC2 This bit is set by hardware and can only...

Page 359: ...tten with 0 CCU6SR2 16 r Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software 0B Interrupt event has not occurred 1B Interrupt event has occurred RES 15 5 r Reserv...

Page 360: ...8 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Interrupt System Table 182 RESET of SCU_IRCON4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RES...

Page 361: ...d be written with 0 CCU6SR2C 16 w Interrupt Flag 1 for CCU6 This bit is set by hardware and can only be cleared by software 0B Interrupt event is not cleared 1B Interrupt event is cleared RES 15 5 w R...

Page 362: ...TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Interrupt System Table 183 RESET of SCU_IRCON4CLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 363: ...e 184 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 WAKEUP 0 r Interrupt Flag for Wakeup This bit is set by hardware and can only be cleared by software 0B...

Page 364: ...Table 185 Field Bits Type Description RES 31 1 r Reserved Returns 0 if read should be written with 0 WAKEUPC 0 w Clear Flag for Wakeup Interrupt This bit is set by hardware and can only be cleared by...

Page 365: ...Timer 6 of GPT Module Interrupt Status 0B No Timer 6 Interrupt has occurred 1B Timer 6 Interrupt has occurred GPT2T5 3 r GPT Module 2 Timer5 Interrupt Status Timer 5 of GPT2 Module Interrupt Status 0B...

Page 366: ...TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Interrupt System Table 186 RESET of SCU_GPT12IRC Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 367: ...Status Timer 6 of GPT Module Interrupt Status 0B Interrupt event is not cleared 1B Interrupt event is cleared GPT2T5C 3 w GPT Module 2 Timer5 Interrupt Status Timer 5 of GPT2 Module Interrupt Status 0...

Page 368: ...TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Interrupt System Table 187 RESET of SCU_GPT12ICLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 369: ...ad should be written with 0 RES 7 2 r Reserved Returns 0 if read should be written with 0 TI 1 rwh Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission...

Page 370: ...ad should be written with 0 RES 7 2 r Reserved Returns 0 if read should be written with 0 TI 1 rwh Serial Interface Transmitter Interrupt Flag Set by hardware at the end of a serial data transmission...

Page 371: ...correctable ECC error has occurred on NVM XRAM 1B Uncorrectable ECC error has occurred on NVM RAM FNMIMAP 5 r NVM Map Error NMI Flag This bit is set by hardware and can only be cleared by software 0B...

Page 372: ...MI has occurred 1B NVM operation complete event has occurred FNMIPLL 1 r PLL NMI Flag This bit is set by hardware and can only be cleared by software 0B No PLL NMI has occurred 1B PLL loss of lock to...

Page 373: ...by the corresponding bits in the SCU_PM module 0B Interrupt event is not cleared 1B Interrupt event is cleared FNMIECCC 6 w ECC Error NMI Flag This flag is cleared automatically by hardware when the...

Page 374: ...ld be cleared after checking and clearing the corresponding event flags 0B Interrupt event is not cleared 1B Interrupt event is cleared FNMINVMC 2 w NVM Operation Complete NMI Flag This bit is set by...

Page 375: ...Mode and Debug Mode the WDT1 is disabled Functional Features Watchdog Timer is operating with a from the system clock fSYS independent clock source fLP_CLK Windowed Watchdog Timer with programmable t...

Page 376: ...Behavior 14 3 Functional Description 14 3 1 Modes of Operation The mode transition from the low power modes WDT1 off to active WDT1 on automatically initializes WDT1 to start in long open window mode...

Page 377: ...trigger the WDT1 operates in a window watchdog mode Configuring of a short open window inside the long open window is not allowed and will also cause a WDT1 reset Figure 73 Windowed Watchdog The first...

Page 378: ...o discard the current window period also within the closed window and immediately starts a short open window The short open window has a fixed length of TSOW independent of the settings of the WDP_SEL...

Page 379: ...ce Module Base Address End Address Note SCUPM 50006000H 50006FFFH SCU_PM Table 193 Register Overview Register Short Name Register Long Name Offset Address Reset Value Watchdog Register Overview SCUPM_...

Page 380: ...H SOW2 two successive Short Open Windows allowed 3H SOW3 three successive Short Open Windows allowed 1 Writing 00H to the WDT_TRIG register will cause a reset WDP_SEL 5 0 rw Watchdog Period Selection...

Page 381: ...bidirectional and can be used as general purpose input output GPIO or to perform alternate input output functions for the on chip peripherals When configured as an output the open drain mode can be se...

Page 382: ...register Px_OD The output multiplexer in front of the output driver enables the port output function to be used for different purposes If the pin is used for general purpose output the multiplexer is...

Page 383: ...ataOut 2 ALTSEL0 Alternate Select Register 0 ALTSEL1 Alternate Select Register 1 AltDataIn PUDEN Pull up Pull down Enable Register DIR Direction Register PUDSEL Pull up Pull down SelectRegister Pull u...

Page 384: ...d to activate an internal weak pull up or pull down device Register P2_PUDSEL selects whether a pull up or the pull down device is activated while register P2_PUDEN enables or disables the pull device...

Page 385: ...ng Name Description Px_DATA Port x Data Register Page 386 Px_DIR Port x Direction Register Page 387 Px_OD Port x Open Drain Control Register Page 389 Px_PUDSEL Port x Pull Up Pull Down Select Register...

Page 386: ...ES 31 8 r Reserved Always read as 0 PP7 7 rwh Portx Pin 7 Data Value 0B Port x pin 7 data value 0 1B Port x pin 7 data value 1 PP6 6 rwh Portx Pin 6 Data Value 0B Port x pin 6 data value 0 1B Port x p...

Page 387: ...0 Data Value 0B Port x pin 0 data value 0 1B Port x pin 0 data value 1 Table 196 RESET of Px_DATA Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3...

Page 388: ...lt or Input driver is enabled default 1B Direction is set to output or Input driver is disabled PP2 2 rw Bidirectional Port x Pin 2 Direction Control or Input only Port x Pin 2 Driver Control 0B Direc...

Page 389: ...on RES 31 8 r Reserved Always read as 0 PP7 7 rwh Port 7 Pin n Open Drain Mode 0B Normal Mode output is actively driven for 0 and 1 state default 1B Open Drain Mode output is actively driven only for...

Page 390: ...bles or disables it The pull up pull down device can be selected pinwise Note The selected pull up pull down device is enabled by setting the respective bit in the Px_PUDEN register PP3 3 rwh Port 3 P...

Page 391: ...ce is selected PP4 4 rwh Pull Up Pull Down Select Port x Bit 4 0B Pull down device is selected 1B Pull up device is selected PP3 3 rwh Pull Up Pull Down Select Port x Bit 3 0B Pull down device is sele...

Page 392: ...or Pull down device is disabled 1B Pull up or Pull down device is enabled PP4 4 rwh Pull Up Pull Down Enable at Port x Bit 4 0B Pull up or Pull down device is disabled 1B Pull up or Pull down device...

Page 393: ...984xQX Microcontroller with LIN and Power Switches for Automotive Applications GPIO Ports and Peripheral I O Table 200 RESET of Px_PUDEN Register Reset Type Reset Values Reset Short Name Reset Mode No...

Page 394: ...output multiplexer which can select up to four output lines This multiplexer can be controlled by the following signals Register Px_ALTSEL0 Register Px_ALTSEL1 Selection of alternate functions is defi...

Page 395: ...eripheral I O Table 201 RESET of Px_ALTSELn n 0 1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 Table 202 Function of Bits Px_ALTSEL0 Pn and Px_...

Page 396: ...urns 0 if read should be written with 0 Px_PDM4 18 16 rw Px x Port Driver Mode Code Driver Strength1 and Edge Shape2 000B Not used 001B Not used 010B Not used 011B Weak Driver 100B Medium Driver 101B...

Page 397: ...used 011B Weak Driver 100B Medium Driver 101B Medium Driver 110B Medium Driver 111B Weak Driver RES 3 r Reserved Returns 0 if read should be written with 0 Px_PDM0 2 0 rw Px x Port Driver Mode Code D...

Page 398: ...15 4 1 2 Port 0 Functions Port 0 alternate function mapping according Table 205 Table 204 Port 0 Registers Register Short Name Register Long Name P0_DATA Port 0 Data Register P0_DIR Port 0 Direction R...

Page 399: ...PO P0_DATA P0 ALT1 T3OUT_0 GPT12 ALT2 EXF21_0 Timer 21 ALT3 UART2_RXDO UART2 P0 1 Input GPI P0_DATA P1 INP1 T13HR_0 CCU6 INP2 UART1_RXD UART1 INP3 T2EX_1 Timer 2 INP4 T21_0 Timer 21 INP5 EXINT0_3 SCU...

Page 400: ...3 T6OUT_1 GPT12 P0 4 Input GPI P0_DATA P4 INP1 SSC1_S_MTSR SSC1 INP2 CC60_0 CCU6 INP3 T21_2 Timer 21 INP4 EXINT2_2 SCU INP5 T3EUDA GPT12 INP6 CCPOS1_1 CCU6 Output GPO P0_DATA P4 ALT1 SSC1_M_MTSR SSC1...

Page 401: ...0H 000000XXH P0_DIR Port 0 Direction Register 04H 00000000H P0_OD Port 0 Open Drain Control Register 08H 00000000H P0_PUDSEL Port 0 Pull Up Pull Down Select Register 0CH 0000003BH P0_PUDEN Port 0 Pull...

Page 402: ...alue 1 PP1_STS 17 r Port 0 Pin 1 Data Value read back of Port Data when IO is configured as output 0B 0 Port 0 pin 1 data value 0 1B 1 Port 0 pin 1 data value 1 PP0_STS 16 r Port 0 Pin 0 Data Value re...

Page 403: ...Trigger enable only valid if IO is configured as output 0B 0 Schmitt Trigger is disabled default 1B 1 Schmitt Trigger is enabled PP3_INEN 19 rw Port 0 Pin 3 Input Schmitt Trigger enable only valid if...

Page 404: ...on is set to output PP3 3 rw Port 0 Pin 3 Direction Control 0B 0 Direction is set to input default 1B 1 Direction is set to output PP2 2 rw Port 0 Pin 2 Direction Control 0B 0 Direction is set to inpu...

Page 405: ...Mode Output is actively driven for 0 and 1 state default 1B Open Drain Mode Output is actively driven only for 0 state PP2 2 rw Port 0 Pin 2 Open Drain Mode 0B Normal Mode Output is actively driven f...

Page 406: ...ull down device is selected 1B Pull up Pull up device is selected default PP2 2 rw Pull Up Pull Down Select Port 0 Bit 2 0B Pull down Pull down device is selected 1B Pull up Pull up device is selected...

Page 407: ...ull up or Pull down device is disabled 1B Enabled Pull up or Pull down device is enabled default PP2 2 rw Pull Up Pull Down Enable at Port 0 Bit 2 0B Disabled Pull up or Pull down device is disabled 1...

Page 408: ...w See Table 216 PP4 4 rw See Table 216 PP3 3 rw See Table 216 PP2 2 rw See Table 216 PP1 1 rw See Table 216 PP0 0 rw See Table 216 Table 213 RESET of P0_ALTSEL0 Register Reset Type Reset Values Reset...

Page 409: ...ee Table 216 PP3 3 rw See Table 216 PP2 2 rw See Table 216 PP1 1 rw See Table 216 PP0 0 rw See Table 216 Table 215 RESET of P0_ALTSEL1 Register Reset Type Reset Values Reset Short Name Reset Mode Note...

Page 410: ...M4 18 16 rw P0 4 Port Driver Mode Code Driver Strength1 and Edge Shape2 000B Strong driver and sharp edge mode 001B Strong driver and medium edge mode 010B Strong driver and soft edge mode 011B Weak D...

Page 411: ...m Driver 001B Not used 010B Not used 011B Weak Driver 100B Medium Driver 101B Medium Driver 110B Medium Driver 111B Weak Driver RES 3 r Reserved Returns 0 if read should be written with 0 P0_PDM0 2 0...

Page 412: ...ions Port 1alternate function mapping according Table 219 Table 218 Port 1 Registers Register Short Name Register Long Name P1_DATA Port 1 Data Register P1_DIR Port 1 Direction Register P1_OD Port 1 O...

Page 413: ...INP4 T4EUDB GPT12 Output GPO P1_DATA P0 ALT1 SSC2_M_SCK SSC2 ALT2 CC61_0 CCU6 ALT3 UART2_TXD UART2 P1 1 Input GPI P1_DATA P1 INP1 T6EUDA GPT12 INP2 T5INB GPT12 INP3 T3EUDC GPT12 INP4 SSC2_S_MTSR SSC2...

Page 414: ...I O P1 4 Input GPI P1_DATA P4 INP1 EXINT2_1 SCU INP2 T21EX_1 Timer 21 INP3 T2INB GPT12 INP4 T5EUDA GPT12 INP5 SSC12_S_MTSR SSC1 2 INP6 CCPOS1_2 CCU6 Output GPO P1_DATA P4 ALT1 CLKOUT_1 SCU ALT2 COUT62...

Page 415: ...r 2CH 00000017H P1_PUDEN Port 1 Pull Up Pull Down Enable Register 30H 00000000H P1_ALTSEL0 Port 1 Alternate Select Register 0 34H 00000000H P1_ALTSEL1 Port 1 Alternate Select Register 1 38H 00000000H...

Page 416: ...ed as output 0B 0 Port 1 pin 0 data value 0 1B 1 Port 1 pin 0 data value 1 RES 15 5 r Reserved Returns 0 if read PP4 4 rwh Port 1 Pin 4 Data Value 0B 0 Port 1 pin 4 data value 0 1B 1 Port 1 pin 4 data...

Page 417: ...is configured as output 0B 0 Schmitt Trigger is disabled default 1B 1 Schmitt Trigger is enabled PP0_INEN 16 rw Port 1 Pin 0 Input Schmitt Trigger enable only valid if IO is configured as output 0B 0...

Page 418: ...ld Bits Type Description RES 31 5 r Reserved Returns 0 if read PP4 4 rw Port 1 Pin 4 Open Drain Mode 0B Normal Mode Output is actively driven for 0 and 1 state default 1B Open Drain Mode Output is act...

Page 419: ...able 224 Field Bits Type Description RES 31 5 r Reserved Returns 0 if read PP4 4 rw Pull Up Pull Down Select Port 1 Bit 4 0B Pull down Pull down device is selected 1B Pull up Pull up device is selecte...

Page 420: ...ault 1B Enabled Pull up or Pull down device is enabled RES 3 r Reserved Returns 0 if read PP2 2 rw Pull Up Pull Down Enable at Port 1 Bit 2 0B Disabled Pull up or Pull down device is disabled default...

Page 421: ...ead PP4 4 rw See Table 229 RES 3 r Reserved Returns 0 if read PP2 2 rw See Table 229 PP1 1 rw See Table 229 PP0 0 rw See Table 229 Table 226 RESET of P1_ALTSEL0 Register Reset Type Reset Values Reset...

Page 422: ...ead PP4 4 rw See Table 229 RES 3 r Reserved Returns 0 if read PP2 2 rw See Table 229 PP1 1 rw See Table 229 PP0 0 rw See Table 229 Table 228 RESET of P1_ALTSEL1 Register Reset Type Reset Values Reset...

Page 423: ...river and sharp edge mode 001B Strong driver and medium edge mode 010B Strong driver and soft edge mode 011B Weak Driver 100B Medium Driver 101B Medium Driver 110B Medium Driver 111B Weak Driver RES 1...

Page 424: ...P1 0 Port Driver Mode Code Driver Strength1 and Edge Shape2 000B Medium Driver 001B Not used 010B Not used 011B Weak Driver 100B Medium Driver 101B Medium Driver 110B Medium Driver 111B Weak Driver 1...

Page 425: ...2 Registers Register Short Name Register Long Name P2_DATA Port 2 Data Register P2_DIR Port 2 Direction Register P2_PUDSEL Port 2 Pull Up Pull Down Select Register P2_PUDEN Port 2 Pull Up Pull Down En...

Page 426: ...ATA P4 INP1 T2EUDB GPT12 INP2 T2_2 Timer 2 INP3 T2EX_2 Timer 2 INP4 CCPOS0_3 CCU6 INP5 CTRAP_2 CCU6 IN XTAL in 1 XTAL P2 5 Input Output GPI P2_DATA P5 INP1 T3EUDB GPT12 INP2 T4EUDC GPT12 INP3 T2_1 Tim...

Page 427: ...User Manual 427 Rev 1 1 2019 03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications GPIO Ports and Peripheral I O 1 configurable by user...

Page 428: ...Port 2 Pull Up Pull Down Select Register 4CH 00000000H P2_PUDEN Port 2 Pull Up Pull Down Enable Register 50H 00000000H P2_DATA Offset Reset Value Port 2 Data Register 40H see Table 234 Field Bits Type...

Page 429: ...value 1 PP0 0 rwh Port 2 Pin 0 Data Value 0B 0 Port 2 pin 0 data value 0 1B 1 Port 2 pin 0 data value 1 Table 234 RESET of P2_DATA Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 430: ...bled Input driver is disabled PP1 1 rw Port 2 Pin 1 Driver Control 0B Enabled Input driver is enabled default 1B Disabled Input driver is disabled PP0 0 rw Port 2 Pin 0 Driver Control 0B Enabled Input...

Page 431: ...default 1B Pull up Pull up device is selected PP2 2 rw Pull Up Pull Down Select Port 2 Bit 2 0B Pull down Pull down device is selected default 1B Pull up Pull up device is selected PP1 1 rw Pull Up P...

Page 432: ...l up or Pull down device is disabled default 1B Enabled Pull up or Pull down device is enabled PP3 3 rw Pull Up Pull Down Enable at Port 2 Bit 3 0B Disabled Pull up or Pull down device is disabled def...

Page 433: ...des Timer Mode Gated Timer Mode Counter Mode Extended capture reload functions via 16 bit capture reload register CAPREL Shared interrupt Node 1 16 2 Introduction The General Purpose Timer Unit blocks...

Page 434: ...4 The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer These registers are listed in Section 16 3 8 1 Figure 83 GPT1 Block Diagram n 2 5 T3 Mode...

Page 435: ...itional Capture Reload register CAPREL supports capture and reload operation with extended functionality These registers are listed in Section 16 4 8 1 Figure 84 GPT2 Block Diagram n 1 4 CAPREL Mode C...

Page 436: ...he auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3 through T3OTL or may be used as capture or reload registers for the core timer T3 The current contents of each tim...

Page 437: ...ogrammed Note When bit T2RC or T4RC in timer control register T2CON or T4CON is set bit T3R will also control start and stop the auxiliary timer s T2 and or T4 Count Direction Control The count direct...

Page 438: ...set or cleared simultaneously In this case both signals to the auxiliary timers carry the same level and no edge will be detected Bit T3OE overflow underflow output enable in register T3CON enables th...

Page 439: ...ore timer T3 is selected by setting bitfield T3M in register T3CON to 000B In Timer Mode T3 is clocked with the module s input clock fGPT divided by two programmable prescalers controlled by bitfields...

Page 440: ...er T3 External Input To enable this operation the associated pin T3IN must be configured as input Figure 88 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 010B the timer is enabled when T3I...

Page 441: ...ition at this line Bitfield T3I in control register T3CON selects the triggering transition see Table 252 Figure 89 Block Diagram of Core Timer T3 in Counter Mode For Counter Mode operation pin T3IN m...

Page 442: ...nts always represent the encoder s current position The interrupt request T3IRQ generation mode can be selected In Rotation Detection Mode T3M 110B an interrupt request is generated each time the coun...

Page 443: ...can be found in Section 16 3 5 As in Incremental Interface Mode two input signals with a 90 phase shift are evaluated their maximum input frequency can be half the maximum count frequency In Incremen...

Page 444: ...on the sensor scurrentposition Dynamicinformation speed acceleration deceleration maybeobtained by measuring the incoming signal periods see Combined Capture Modes on Page 480 MCT04373 Forward Jitter...

Page 445: ...entically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers Note The auxilia...

Page 446: ...odes is almost identical with the core timer s operation with very few exceptions Additionally some combined operating modes can be selected Timers T2 and T4 in Timer Mode Timer mode for an auxiliary...

Page 447: ...or 011B Bit TxM 0 TxCON 3 selects the active level of the gate input Note A transition of the gate signal at line TxIN does not cause an interrupt request Figure 95 Block Diagram of an Auxiliary Time...

Page 448: ...selects the triggering transition see Table 253 Figure 96 Block Diagram of an Auxiliary Timer in Counter Mode Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 w...

Page 449: ...flow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer As long as bit T3OTL is not modified by software it represents the state of t...

Page 450: ...evant for capture mode and must be cleared TxI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independently of its run flag T2R or T4R Figure 98 GPT1 Auxiliary...

Page 451: ...o provide 2 fold or 4 fold resolution of the encoder input Figure 99 Block Diagram of an Auxiliary Timer in Incremental Interface Mode The operation of the auxiliary timers T2 and T4 in Incremental In...

Page 452: ...will NOT trigger the counter function of T2 T4 To ensure that a transition of the reload input signal applied to TxIN is recognized correctly its level must be held high or low for a minimum number of...

Page 453: ...selecting the same reload trigger event for both auxiliary timers should be avoided In such a case both reload registers would try to load the core timer at the same time If this combination is selec...

Page 454: ...seen from the following formula 16 1 The effective count frequency depends on the common module clock prescaler factor F BPS1 as well as on the individual input prescaler factor 2 TxI Table 251 summar...

Page 455: ...able bit is set In Reload Mode upon a trigger signal T3 is loaded with the contents of the respective timer T2 or T4 and the respective interrupt request flag in register GPT12E_T2 or GPT12E_T4 is set...

Page 456: ...57 GPT12E_T4 Timer T4 Count Register 28H Page 457 GPT1 Registers GPT1 Core Timer T3 Control Register GPT12E_T3CON Timer T3 Control Register 0CH Page 458 GPT1 Registers GPT1 Auxiliary Timers T2 T4 Cont...

Page 457: ...alue of the timer T2 Table 244 RESET of GPT12E_T2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 GPT12E_T3 Offset Reset Value Timer T3 Count Regi...

Page 458: ...fset Reset Value Timer T3 Control Register 0CH see Table 247 Field Bits Type Description RES 31 16 r Reserved Read as 0 should be written with 0 T3DIR 15 rh Timer T3 Rotation Direction Flag 0B Up Time...

Page 459: ...Timer T3 External Up Down Enable1 0B T3UD Count direction is controlled by bit T3UD input T3EUD is disconnected 1B T3EUD Count direction is controlled by input T3EUD T3UD 7 rw Timer T3 Up Down Control...

Page 460: ...QX Microcontroller with LIN and Power Switches for Automotive Applications General Purpose Timer Units GPT12 Table 247 RESET of GPT12E_T3CON Register Reset Type Reset Values Reset Short Name Reset Mod...

Page 461: ...Change A change of count direction was detected T2EDGE 13 rwh Timer T2 Edge Detection The bit is set each time a count edge is detected T2EDGE must be cleared by software 0B No count No count edge was...

Page 462: ...de with gate active high 100B Reload Mode 101B Capture Mode 110B Incremental Interface Mode Rotation Detection Mode 111B Incremental Interface Mode Edge Detection Mode T2I 2 0 rw Timer T2 Input Parame...

Page 463: ...upts in Incremental Interface Mode is enabled 1B Disabled Interrupt generation for T4CHDIR and T4EDGE interrupts in Incremental Interface Mode is disabled CLRT3EN 11 rw Clear Timer T3 Enable Enablesth...

Page 464: ...rameter Selection Depends on the operating mode see respective sections for encoding Table 251 for Timer Mode and Gated Timer Mode Table 252 for Counter Mode Table 254 for Incremental Interface Mode 1...

Page 465: ...T2 T4 Input Edge Selection Counter Mode T2I T4I Triggering Edge for Counter Increment Decrement X00B None Counter Tx is disabled 001B Positive transition rising edge on TxIN 010B Negative transition...

Page 466: ...18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications General Purpose Timer Units GPT12 16 3 8 5 GPT1 Timer Interrupt Control Registers The Interrupt Control and Status...

Page 467: ...the contents of timer T5 or to reload timer T6 A special mode facilitates the use of register CAPREL for both functions at the same time This mode allows frequency multiplication The capture function...

Page 468: ...till be used to reverse the actual count direction as shown in Table 264 The count direction can be changed regardless of whether or not the timer is running Note When pin TxEUD is used as external co...

Page 469: ...Timer T6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register T6CON to 000B In this mode T6 is clocked with the module s input clock fGPT divided by two progr...

Page 470: ...rnal Input To enable this operation the associated pin T6IN must be configured as input Figure 105 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M 010B the timer is enabled when T6IN shows a...

Page 471: ...his line Bitfield T6I in control register T6CON selects the triggering transition see Table 267 Figure 106 Block Diagram of Core Timer T6 in Counter Mode For Counter Mode operation pin T6IN must be co...

Page 472: ...dividual configurations for timer T5 are determined by its control register T5CON Some bits in this register also control the function of the CAPREL register Note that functions which are present in a...

Page 473: ...T5 in Timer Mode Timer Mode for the auxiliary timer T5 is selected by setting its bitfield T5M in register T5CON to 000B Figure 107 Block Diagram of Auxiliary Timer T5 in Timer Mode Timer T5 in Gated...

Page 474: ...on at its external input line T5IN or by a transition of timer T6 s toggle latch T6OTL The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a nega...

Page 475: ...ed to clock the auxiliary timer 32 bit Timer Counter If both a positive and a negative transition of T6OTL are used to clock the auxiliary timer this timer is clocked on every overflow underflow of th...

Page 476: ...alue to select a trigger signal In capture mode the contents of the auxiliary timer T5 are latched into register CAPREL in response to a signal transition at the selected external input pin s Bit CT3...

Page 477: ...an still be used to clear timer T5 and or T6 or as external interrupt input s This interrupt is controlled by the CAPREL interrupt control register GPTM1IEN and GPTM1IRC When capture triggers T3IN or...

Page 478: ...6CON In reload mode the core timer T6 is reloaded with the contents of register CAPREL triggered by an overflow or underflow of T6 This will not activate the interrupt request line CRIRQ associated wi...

Page 479: ...pin CAPIN When an external event occurs the contents of timer T5 are latched into register CAPREL and timer T5 is cleared T5CLR 1 Thus register always contains the correct time between two events meas...

Page 480: ...r a 10 kHz input signal applied at CAPIN while T6 counts up from FF9CH through FFFFH to 0000H So the overflow occurs after 100 timing ticks of T6 and the actual output frequency at T6OUT then is the e...

Page 481: ...ear the corresponding service request flags and re initialize those registers T5 T6 CAPREL that might be affected by a count capture reload event Internal Count Clock Generation In Timer Mode and Gate...

Page 482: ...its interrupt request flag in register GPT2_T5 or GPT2_T6I will be set This will cause an interrupt to the respective timer interrupt vector if the respective interrupt enable bit is set Table 257 GPT...

Page 483: ...for the CAPREL register All interrupt control registers have the same structure described in section Interrupt Control 16 4 8 GPT2 Registers 16 4 8 1 GPT2 Timer Registers Timer 5 Count Register Timer...

Page 484: ...t Values Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 GPT12E_CAPREL Offset Reset Value Capture Reload Register 1CH see Table 261 Field Bits Type Description RES 31 16 r Reserve...

Page 485: ...T 2 10B 16 fGPT 16 11B 8 fGPT 8 T6OTL 10 rwh Timer T6 Overflow Toggle Latch Toggles on each overflow underflow of T6 Can be set or cleared by software see separate description T6OE 9 rw Overflow Under...

Page 486: ...e 265 for Timer Mode and Gated Timer Mode Table 267 for Counter Mode 1 See Table 264 for encoding of bits T6UD and T6UDE Table 262 RESET of GPT12E_T6CON Register Reset Type Reset Values Reset Short Na...

Page 487: ...Down Enable3 0B T5UD Count direction is controlled by bit T5UD input T5EUD is disconnected 1B T5EUD Count direction is controlled by input T5EUD T5UD 7 rw Timer T2 Up Down Control3 0B Up Timer T5 cou...

Page 488: ...0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Table 265 GPT2 Overall Prescaler Factors for Internal Count Clock Timer Mode and Gated Timer Mode Individual Prescaler for Tx Common Prescal...

Page 489: ...on falling edge of T6 toggle latch T6OTL 111B Any transition rising or falling edge of T6 toggle latch T6OTL Table 267 GPT2 Core Timer T6 Input Edge Selection Counter Mode T6I Triggering Edge for Coun...

Page 490: ...d trigger from T3 is selected 11B CAPIND Signal CAPIND Read trigger from T2 or T3 or T4 is selected IST6EUD 13 rw Input Select for T6EUD 0B T6EUDA Signal T6EUDA is selected 1B T6EUDB Signal T6EUDB is...

Page 491: ...d 10B T3EUDC Signal T3EUDC is selected 11B T3EUDD Signal T3EUDD is selected IST3IN 3 2 rw Input Select for T3IN 00B T3INA Signal T3INA is selected 01B T3INB Signal T3INB is selected 10B T3INC Signal T...

Page 492: ...tification Number This bitfield defines the module identification number 58H GPT12E MOD_REV 7 0 r Module Revision Number MOD _REV defines the revision number The value of a module revision starts with...

Page 493: ...Figure 114 GPT Module Interfaces Note The GPT12E output signal T6OFL is connected to the CAPCOM2 input TOUF and to the GSC The following table Table 270 GPT12 showsthe digitalconnectionsofthe GPT12mo...

Page 494: ...input signals for timer T4 T4EUDB P1 0 I T4EUDC P2 5 I T4EUDD P2 6 I T4IRQ ICU SCU O interrupt request from timer T4 T5INA P0 5 I count input signals for timer T5 T5INB P1 1 I T5EUDA P1 4 I direction...

Page 495: ...field PC in the respective port control register must be 1xxxB Note For a description of the port control registers please refer to chapter Parallel Ports Interrupts The GPT12 has six interrupt reques...

Page 496: ...or U S ART 17 2 Introduction Two functionally identical timers are implemented Timer 2 and 21 The description refers to Timer 2 only but applies to Timer 21 as well The timer modules are general purpo...

Page 497: ...s further classified into two categories depending upon the DCEN control bit Table 271 Timer2 and Timer21 Modes Mode Description Auto reload Up Down Count Disabled Count up only Start counting from 16...

Page 498: ...negative positive edge chosen by T2MOD EDGESEL at input pin T2EX If an overflow caused the reload the overflow flag TF2 is set If a negative positive transition at pin T2EX caused the reload bit EXF2...

Page 499: ...to the occurrence of an overflow condition A logic 0 at pin T2EX sets the Timer 2 to down counting mode The timer counts down and underflows when the THL2 value reaches the value stored at register R...

Page 500: ...test value of the timer register is always captured If bit T2RHEN is set Timer 2 is started by first falling edge rising edge at pin T2EX which is defined by bit T2REGS If bit EXEN2 is set bit EXF2 is...

Page 501: ...ulting interrupt could therefore be used in the product as an external falling rising edge triggered interrupt 17 4 Timer 2 Register Definition All Timer 2 and Timer 21 register names described in the...

Page 502: ...Timer 2 External Start is disabled 1B ENABLED Timer 2 External Start is enabled EDGESEL 5 rw Edge Select in Capture Mode Reload Mode 0B FALLING The falling edge at Pin T2EX is selected 1B RISING The...

Page 503: ...mer21 DCEN 0 rw Up Down Counter Enable 0B DISABLED Up Down Counter function is disabled 1B ENABLED Up Down Counter function is enabled and controlled by pin T2EX Up 1 Down 0 Table 274 Reset of T2_MOD...

Page 504: ...External Flag In Capture Reload Mode this bit is set by hardware when a negative positive transition occurs at pin T2EX if bit EXEN2 1 This bit must be cleared by software Note When bit DCEN 1 in auto...

Page 505: ...alues Reset Short Name Reset Mode Note RESET_TYPE_3 00000000H RESET_TYPE_3 T2_ICLR Offset Reset Value Timer 2 Interrupt Clear Register 18H see Table 276 Field Bits Type Description RES 31 8 r Reserved...

Page 506: ...escription RES 31 2 r Reserved Always read as 0 TF2EN 1 rw Overflow Underflow Interrupt Enable 0B DISABLE Overflow underflow interrupt 1B ENABLE Overflow underflow interrupt EXF2EN 0 rw External Inter...

Page 507: ...t priority and is updated by hardware during capture mode These contents are loaded into the timer register upon an overflow condition if CP_RL2 0 If CP_RL2 1 this register is loaded with the current...

Page 508: ...RES 31 16 r Reserved Always read as 0 T2H 15 8 rw Timer 2 Value These bits indicate the current timer value T2 15 8 Note Timer 2 can be updated by software highest priority and is updated by hardware...

Page 509: ...connected directly to the CPU s Interrupt Controller but via the System Control Unit SCU The General Purpose IO GPIO Port provides the interface from the Timer2 and Timer21 to the external world The...

Page 510: ...Interface T21_interface vsd t21_ext_trigger t21_adc_trigger SCU_DM Module Kernel TIMER21 Module Kernel T21_IRQ Clock Control Address Decoder fT21 Interrupt Control AHB T2EX PortControl T21EX_0 EXF2 T...

Page 511: ...12 Block Features Three capture compare channels each channel can be used either as capture or as compare channel Generation of a three phase PWM supported six outputs individual signals for High Side...

Page 512: ...pare channel The T12 channels can independently generate PWM signals or accept capture triggers or they can jointly generate control signal patterns to drive AC motors or inverters A rich set of statu...

Page 513: ...ontrol PortControl Compare Compare 2 2 Compare Output Select 3 Hall Input Output Select 1 Trap Input 3 Capture T13 CC63 Start 2 1 Multi channel Control Trap Control Dead Time Control CC60 CC61 Compare...

Page 514: ...eneration the T12 block offers options for individual compare and capture functions as well as dead time control and hysteresis like compare mode This section provides information about T12 overview s...

Page 515: ...eached the period value defined by T12PR In Center Aligned mode the count direction of T12 is set from up to down after it has reached the period value please note that in this mode T12 exceeds the pe...

Page 516: ...The start or stop of T12 is controlled by the Run bit T12R that can be modified by bits in register TCTR4 The run bit can be set cleared by software via the associated set clear bits T12RS or T12RR i...

Page 517: ...280 The prescaler of T12 is cleared while T12 is not running TCTR0 T12R 0 to ensure reproducible timings and delays In Counter Mode timer T12 counts one step If a 1 is written to TCTR4 T12CNT and PIS...

Page 518: ...ch T12_PM while counting upwards CDIR 0 the counting direction control bit CDIR is changed to downwards CDIR 1 with the next counting step When reaching the value 0001H one match T12_OM while counting...

Page 519: ...changes with the next timer clock event after the one match or the period match Therefore the timer continues counting in the previous direction for one cycle before actually changing its direction se...

Page 520: ...gned mode T12R is cleared when the timer becomes zero after having reached the period value see Figure 125 Figure 125 Single Shot Operation in Edge Aligned Mode In Center Aligned mode the period is fi...

Page 521: ...double register structure the actual compare register CC6xR feeding the comparator and an associated shadow register CC6xSR that is preloaded by software and transferred into the compare register whe...

Page 522: ...ed when a compare match is detected while counting upwards whereas the compare interrupt event CC6x_F is signaled when a compare match is detected while counting down The actual setting of a State Bit...

Page 523: ...de with the next T12 clock fT12 after a zero match AND NO parallel compare match when T12 is counting up Figure 129 Compare Operation Edge Aligned Mode Figure 131 illustrates some more examples for co...

Page 524: ...remains at 1 producing a 100 duty cycle signal In this case the compare rule zero match AND compare match is in effect Example f shows the transition to a duty cycle of 0 The new compare value is set...

Page 525: ...oller with LIN and Power Switches for Automotive Applications Capture Compare Unit 6 CCU6 Figure 132 Three Channel Compare Waveforms CCU6_MCT05518 Period Value Up Down Down Up Down Zero CC60R CC61R CC...

Page 526: ...iming related behavior to a hysteresis controller A standard hysteresis controller detects if a value exceeds a limit and switches its output according to the compare result Depending on the operating...

Page 527: ...compare channel For example if the High Side switch should be active while the T12 counter value is above the compare value State Bit 1 then the low side switch should be active while the counter valu...

Page 528: ...ogress active This avoids an unintentional additional dead time if a State Bit CC6xST changes too early A disabled dead time counter is always considered as passive and does not delay any edge of CC6x...

Page 529: ...after a change of the corresponding State Bit CC6xST The user can select independently for each output signal CC6xO and COUT6xO if it should be active before or after the compare value has been reach...

Page 530: ...state regardless of the state of the other signals that are enabled Only if all enabled signals are in active state the modulated output shows an active state If no modulation input is enabled the ou...

Page 531: ...utput Modulation for Compare Channel CC60 CCU6_MCA05543 CC60 Output Modulation CC60 CC60_O T12MODEN0 TRPEN0 PSL0 active passive T13 Block T12 Block Dead Time Multi Channel Mode CC63_O T13MODEN0 TRPS T...

Page 532: ...ents of Timer T12 are captured into register CC6xSR Figure 137 Capture Mode 1 Block Diagram Capture Modes 2 3 and 4 are shown in Figure 138 They differ only in the active edge causing the capture oper...

Page 533: ...or Automotive Applications Capture Compare Unit 6 CCU6 Figure 138 Capture Modes 2 3 and 4 Block Diagram CCU6_MCB05523 fT12 Edge Detect Capture Mode Selection State Bit CC6xST CC6xIN To Interrupt Logic...

Page 534: ...ate Bit CC6xST is set to 1 when the selected capture trigger event at signal CC6xIN or CCPOSx has occurred The State Bit is not cleared by hardware but can be cleared by software In addition appropria...

Page 535: ...or Automotive Applications Capture Compare Unit 6 CCU6 1101B 8 CC6xIN Falling CC6xR CCPOSx Falling CC6xSR 1110B 9 CC6xIN Any CC6xR CCPOSx Any CC6xSR 1111B reserved no capture or compare action Table 2...

Page 536: ...ext PWM period can run with a new set of parameters The generation of this signal is requested by software via bit TCTR0 STE12 set by writing 1 to the write only bit TCTR4 T12STR cleared by writing 1...

Page 537: ...ne channel in compare mode A 16 bit up counter is connected to a channel register via a comparator that generates a signal when the counter contents match the contents of the channel register A variet...

Page 538: ...eriod Match is generated and T13 is cleared to 0000H with the next T13 clock edge The Period Register receives a new period value from its Shadow Period Register T13PS that is loaded via software The...

Page 539: ...top the timer The generation of the T13 shadow transfer control signal T13_ST is enabled via bit STE13 This bit can be set or cleared by software indirectly through its associated set reset control bi...

Page 540: ...able 284 The prescaler of T13 is cleared while T13 is not running TCTR0 T13R 0 to ensure reproducible timings and delays In Counter Mode timer T13 counts one step If a 1 is written to TCTR4 T13CNT and...

Page 541: ...le for the T13 counter The counter is cleared with the next T13 clock edge if a Period Match is detected The counting direction is always upwards The behavior of T13 is illustrated in Figure 143 Figur...

Page 542: ...he figure shows an example in which T13 is clocked with half the frequency of T12 Figure 145 Synchronization of T13 to T12 Compare Match Bit field T13TEC selects the trigger event to start T13 automat...

Page 543: ...e Compare Unit 6 CCU6 Table 286 T12 Trigger Event Additional Specifier T13TED Selected Event Specifier 00B Reserved no action 01B Selected event is active while T12 is counting up CDIR 0 10B Selected...

Page 544: ...olding the status of the compare operation Figure 146 gives an overview on the logic for the State Bit Figure 146 T13 State Bit Block Diagram A compare interrupt event CM_63 is signaled when a compare...

Page 545: ...wer Switches for Automotive Applications Capture Compare Unit 6 CCU6 with the next T13 clock fT13 after a zero match AND NO parallel compare match Figure 147 T13 Compare Operation CCU6_MCT05533 fT13 Z...

Page 546: ...ECT13O 1 and is at passive state the modulated is also in passive state If the modulation input is not enabled the output is in passive state If the Trap State is active TRPS 1 then the output enable...

Page 547: ...rameters The next PWM period can run with a new set of parameters The generation of this signal is requested by software via bit TCTR0 STE13 set by writing 1 to the write only bit TCTR4 T13STR cleared...

Page 548: ...s Capture Compare Unit 6 CCU6 Figure 150 T13 Shadow Register Overview CCU6_MCA05547 Compare Register CC63R Compare Shadow Register CC63SR Period Register T13PR Period Shadow Register T13PR T13IM T13IM...

Page 549: ...uts and the T13 related output facilitate a flexible adaptation to the application needs There are a number of different ways to exit the Trap State This offers SW the option to select the best operat...

Page 550: ...crocontroller with LIN and Power Switches for Automotive Applications Capture Compare Unit 6 CCU6 Figure 152 Trap State Synchronization with TRM2 0 CCU6_MCT05542 T12 Count T13 Count TRPF TRPS TRPS TRP...

Page 551: ...e the update of MCMP to a PWM generated by T12 or T13 bit field SWSYN allows the selection of the synchronization event leading to the transfer from MCMPS to MCMP Due to this structure an update takes...

Page 552: ...CM_CHE detected at input signals CCPOSx without additional delay 010B T13 Period Match T13_PM 011B T12 One Match while counting down T12_OM and CDIR 1 100B T12 Compare Channel 1 Event while counting...

Page 553: ...Hall pattern EXPH and the corresponding output pattern MCMP A new Modulation pattern is output when the sampled Hall inputs match the expected ones EXPH To detect the next rotation phase segment for b...

Page 554: ...ring a PWM period This can be used to sample the Hall inputs when the switching noise due to PWM does not disturb the Hall input signals If neither the delay function of Dead Time Counter 0 is not use...

Page 555: ...h while counting up T12_PM and CDIR 0 101B A T12 One Match while counting down T12_OM and CDIR 1 110B A T12 Compare Match of compare channel CC61 while counting up CM_61 and CDIR 0 111B A T12 Compare...

Page 556: ...pled Hall pattern matches the value programmed in EXPH the detected transition was the expected event correct Hall event CM_CHE and the MCMP value has to change IfthesampledHallpatternmatchesneitherCU...

Page 557: ...request generation is triggered by the set signal for the flag That means a request can be generated even if the flag is already set There is no need to clear the flag in order to enable further inte...

Page 558: ...e as first time out criterion A second time out criterion can be built by the T12 period match event Figure 157 T12 Block in Hall Sensor Mode The signal CM_CHE from the Hall compare logic is used to t...

Page 559: ...synchronization of the next multi channel state to the PWM source to avoid spikes on the output lines see Section 18 6 This compare function of channel CC61 can be used as a phase delay from the posi...

Page 560: ...status bit to be able to generate another interrupt The interrupt flag can be cleared by SW by writing to the corresponding bit in register ISR If enabled by the related interrupt enable bit in regist...

Page 561: ...upt Reset Register ISR Interrupt Enable Register IEN Interrupt Status Register IS T12 Counter T12_PM T12_OM T12 Capture Compare Channels CC6x CC6x_R CC6x_F T13 Counter T13_PM T13 Compare Channel CC63...

Page 562: ...ut select registers PISEL0 and PISEL2 This permits to adapt the pin functionality of the device to the application requirements The output pins for the module output signals are chosen in the ports No...

Page 563: ...60 14H 0000H CCU6_CC61SR Capture Compare Shadow Register for Channel CC61 18H 0000H CCU6_CC62SR Capture Compare Shadow Register for Channel CC62 1CH 0000H CCU6_T12PR Timer T12 Period Register 24H 0000...

Page 564: ...rol Register 60H 0000H CCU6 Register Description Multi Channel Modulation Control Registers CCU6_MCMOUTS Multi Channel Mode Output Shadow Register 08H 0000H CCU6_MCMCTR Multi Channel Mode Control Regi...

Page 565: ..._3 ISPOS1 11 10 rw Input Select for CCPOS1 This bit field defines the port pin that is used for the CCPOS1 input signal 00B CCPOS1_0 The input pin for CCPOS1_0 01B CCPOS1_1 The input pin for CCPOS1_1...

Page 566: ...CC60_1 10B Reserved Reserved 11B Reserved Reserved Table 292 RESET of CCU6_PISEL0 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000H RESET_TYPE_3 CCU6_PISEL2 Offset R...

Page 567: ...not taken into account 10B Rising edge The timer T13 is counting each rising edge detected in the selected T13HR signal 11B Falling Edge The timer T13 is counting each falling edge detected in the sel...

Page 568: ...s too late The value 1000B must be programmed to MSEL0 MSEL1 and MSEL2 if the hall signals are used In this mode the contents of timer T12 are captured in CC60 and T12 is reset after the detection of...

Page 569: ...SYNC 14 12 rw Hall Synchronization Bit field HSYNC defines the source for the sampling of the Hall input pattern and the comparison to the current and the expected Hall pattern bit fields In all modes...

Page 570: ...rammed to Hall Sensor mode 1001BHysteresis like mode see Table 295 101XBMulti Input Capture modes see Table 296 11XXBMulti Input Capture modes see Table 296 MSEL61 7 4 rw Capture Compare Mode Selectio...

Page 571: ...an be used for I O No capture action 0001BPin CC6n pin COUT6n Compare output on pin CC6n pin COUT6n can be used for I O No capture action 0010BPin COUT6n Pin CC6n Compare output on pin COUT6n pin CC6n...

Page 572: ...egisters for T12 The values stored in CC60R are compared all three channels in parallel to the counter value of T12 In capture mode the current value of the T12 counter register is captured by registe...

Page 573: ...by registers CC62R if the corresponding capture event is detected Field Bits Type Description CCV 15 0 rh Channel 0 Capture Compare Value In compare mode the bit fields CCV contain the values that are...

Page 574: ...In compare mode the bit fields CCV contain the values that are compared to the T12 counter value In capture mode the captured value of T12 can be read from these registers Table 302 RESET of CCU6_CC6...

Page 575: ...ister transfer from register CC62SR The corresponding shadow registers CC62SR can be read and written by software In capture mode the value of the T12 counter register can also be captured by register...

Page 576: ...but by bit DTRES Field Bits Type Description CCS 15 0 rwh Shadow Register for Channel 2 Capture Compare Value Incomparemode thecontentsofbitfieldCCSaretransferredto the bit field CCV for the correspon...

Page 577: ...2 enables and disables the dead time generation for compare channel 2 of timer T12 0B Disabled Dead time generation is disabled The corresponding outputs switch from the passive state to the active st...

Page 578: ...ual compare status without any delay 1B Enabled Dead timegenerationisenabled Thecorresponding outputs switch from the passive state to the active state according to the compare status with the delay p...

Page 579: ...nly edge aligned mode counting up Register T13PR contains the period value for timer T13 The period value is compared to the actual counter value of T13 and the resulting counter actions depend on the...

Page 580: ...Unit 6 CCU6 Field Bits Type Description T13PV 15 0 rwh T13 Period Value The value T13PV defines the counter value for T13 which leads to a period match On reaching this value the timer T13 is set to...

Page 581: ...ure Compare Register for Channel CC63 00H see Table 309 Field Bits Type Description CCV 15 0 rh Channel CC63 Compare Value Low Byte The bit field CCV contains the value that is compared to the T13 cou...

Page 582: ...3 output is inverted for further modulation COUT63PS 14 rwh Passive State Select for Compare Outputs Bits COUT6xPS select the state of the corresponding compare channel which is considered to be the p...

Page 583: ...fined in register PSLR is driven by the output pin Bits CC6xPS are related to T12 bit COUT63PS is related to T13 These bits have shadow bits and are updated in parallel to the capture compare register...

Page 584: ...PSLR is driven by the output pin Bits COUT6xPS x 0 1 2 are related to T12 bit COUT63PS is related to T13 These bits have shadow bits and are updated in parallel to the capture compare registers of T12...

Page 585: ...it CCPOS1 indicate the value of the input Hall pattern that has been compared to the current and expected value The value is sampled when the event hcrdy Hall compare ready occurs 0B Zero The input CC...

Page 586: ...r Incomparemode thecountervalueisgreaterthanor equal to the compare value In capture mode the selected edge has been detected CC60ST 0 rh Capture Compare State Bits BitsCC6xSTmonitorthestateofthecaptu...

Page 587: ...ee Table 313 MCC61R 9 w Capture Compare Status Modification Bit 1 Reset This bit is used to reset the corresponding CC61ST bits by software This feature allows the user to individually change the stat...

Page 588: ...ipulation of CC61ST bits by a single data write action Functionality see Table 313 MCC60S 0 w Capture Compare Status Modification Bit 0 Set This bit is used to set the corresponding CC60ST bits by sof...

Page 589: ...is detected Bit STE13 is cleared by hardware after the shadow transfer A T13 shadow transfer event is a period match 0B Disabled The shadow register transfer is disabled 1B Enabled The shadow register...

Page 590: ...the shadow transfer of the T12 period value the compare values and passive state select bits and levels from their shadow registers to the actual registers if a T12 shadow transfer event is detected B...

Page 591: ...timer T12 which is derived from the peripheral clock according to the equation fT12 fCCU 2 T12CLK 000B 1 fT12 fCCU 001B 2 fT12 fCCU 2 010B 4 fT12 fCCU 4 011B 8 fT12 fCCU 8 100B 16 fT12 fCCU 16 101B 3...

Page 592: ...on RES 15 12 r Reserved Returns 0 if read T13RSEL 11 10 rw Timer T13 External Run Selection Bit field T13RSEL defines the event of signal T13HR that can set the run bit T13R by hardware 00B Disabled T...

Page 593: ...any T12 compare event on the channels 0 1 or 2 101B Period match set T13R upon a period match of T12 110B Zero match set T13R upon a zero match of T12 while counting up 111B CCPOSx set T13R on any ed...

Page 594: ...13R Furthermore the timers can be reset while running and bits STE12 and STE13 can be controlled by software Reading these bits always returns 0 CCU6_TCTR4 Offset Reset Value Timer Control Register 4...

Page 595: ...set enabling the shadow transfer T12CNT 5 w Timer T12 Count Event 0B No action 1B Count If enabled PISEL2 timer T12 counts one step RES 4 r Reserved Returns 0 if read DTRES 3 w Dead Time Counter Rese...

Page 596: ...bled 1B Enabled The alternate output function COUT63 is enabled for the PWM signal generated by T13 RES 14 r Reserved Returns 0 if read T13MODEN 13 8 rw T13 Modulation Enable Setting these bits enable...

Page 597: ...nel pattern according to bit field MCMOUT is enabled RES 6 r Reserved Returns 0 if read T12MODEN 5 0 rw T12 Modulation Enable Setting these bits enables the modulation of the corresponding compare cha...

Page 598: ...tionality for T13 is enabled The timer T13 PWM output signal is set to the passive state while TRPS 1 TRPEN 13 8 rw Trap Enable Control Setting these bits enables the trap functionality for the follow...

Page 599: ...ndition according to TRPM10 is detected TRPM10 1 0 rw Trap Mode Control Bits 1 0 These two bits define the behavior of the selected outputs when leaving the trap state after the trap condition has bec...

Page 600: ...short pulses when leaving the trap state The combination TRPM1 TRPM0 leads to 00B The trap state is left return to normal operation according to TRPM2 when a zero match of T12 while counting up is de...

Page 601: ...ctually used values can be read attribute rh whereas the shadow bits can only be written attribute w CCU6_PSLR Offset Reset Value Passive State Level Register 50H see Table 320 Field Bits Type Descrip...

Page 602: ...hat can be read and written for register MCMOUT which indicates the currently active signals Table 320 RESET of CCU6_PSLR Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3...

Page 603: ...est for MCMPS Settingthisbitduringawriteactionleadstoanimmediateupdateof bit field MCMP by the value written to bit field MCMPS This functionality permits an update triggered by software When read thi...

Page 604: ...in order to detect the occurrence of the next desired expected hall pattern or a wrong pattern If the currenthallpatternat the hallinput pinsisequalto the bit field EXPH bit CHE correct hall event is...

Page 605: ...utput CC60 Bit 1 multi channel state for output COUT60 Bit 2 multi channel state for output CC61 Bit 3 multi channel state for output COUT61 Bit 4 multi channel state for output CC62 Bit 5 multi chann...

Page 606: ...w Shadow Transfer Enable for T12 Upcounting This bit enables the shadow transfer T12_ST if flag MCMOUT R is set or becomes set while a T12 period match is detected while counting up 0B No action 1B En...

Page 607: ...transfer takes place synchronously with an event selected in bit field SWSYN 000B No request no trigger request will be generated 001B Correct pattern correct hall pattern on CCPOSx detected 010B T13...

Page 608: ...capture interrupts are also generated while the timer T12 is stopped Note Not all bits in register IS can generate an interrupt Other status bits have been added that have a similar structure for thei...

Page 609: ...ven during the passive state is defined by the corresponding bit in register PSLR Bit TRPS 1 and TRPF 0 can occur if the trap condition is no longer active but the selected synchronization has not yet...

Page 610: ...unting up In capture mode a rising edge has been detected at the input CC62 0B Not occurred The event has not yet occurred since this bit has been reset for the last time 1B Detected The event describ...

Page 611: ...the last time 1B Detected The event described above has been detected Table 324 RESET of CCU6_IS Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 0000H RESET_TYPE_3 CCU6_...

Page 612: ...action 1B Set Bit T12PM in register IS will be set ST12OM 6 w Set Timer T12 One Match Flag 0B No action 1B Set Bit T12OM in register IS will be set SCC62F 5 w Set Capture Compare Match Falling Edge Fl...

Page 613: ...ll be reset RES 11 r Reserved Returns 0 if read RTRPF 10 w Reset Trap Flag 0B No action 1B Reset Bit TRPF in register IS will be reset not taken into account while input CTRAP 0 and TRPPEN 1 RT13PM 9...

Page 614: ...et RCC61R 2 w Reset Capture Compare Match Rising Edge Flag 0B No action 1B Reset Bit CC61R in register IS will be reset RCC60F 1 w Reset Capture Compare Match Falling Edge Flag 0B No action 1B Reset B...

Page 615: ...tion for bit WHE in register IS occurs 1B Interrupt An interrupt will be generated if the set condition for bit WHE in register IS occurs The interrupt line that will be activated is selected by bit f...

Page 616: ...ge Interrupt Enable for Channel 2 0B No interrupt No interrupt will be generated if the set condition for bit CC62F in register IS occurs 1B Interrupt An interrupt will be generated if the set conditi...

Page 617: ...egister ISoccurs Theinterruptlinethatwill be activated is selected by bit field INPCC60 ENCC60R 0 rw Capture Compare Match Rising Edge Interrupt Enable for Channel 0 0B No interrupt No interrupt will...

Page 618: ...or Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit TRPF if enabled by bit ENTRPF or for bit WHE if enabled by bit ENWHE 00B SR0 Interrupt...

Page 619: ...ted 10B SR2 Interrupt output line SR2 is selected 11B SR3 Interrupt output line SR3 is selected INPCC60 1 0 rw Interrupt Node Pointer for Channel 0 Interrupts This bit field defines the interrupt outp...

Page 620: ...t implementation details The CCU6 kernel is clocked on PCLK frequency where fCCU fPCLK Debug Suspend of Timers The timers of CCU6 T12 and T13 can be suspended immediately when OCDS enters Monitor Mode...

Page 621: ...ule Interrupt Controller Clock Control Address Decoder fCCU CCU6 Module Kernel Port Control CC62 COUT62 COUT61 COUT63 CC60 COUT60 CCPOS2 CC61 CTRAP CCPOS0 CCPOS1 SRC0 SRC1 SRC2 SRC3 T12HRA B T13HRA B...

Page 622: ...modes by the incoming start bit if REN 1 The serial interface also provides interrupt requests when transmission or reception of the frames has been completed The corresponding interrupt request flags...

Page 623: ...x Rx IRQ s 19 3 1 Mode 0 8 Bit Shift Register Fixed Baud Rate In mode 0 the serial port behaves as an 8 bit shift register Data is shifted in through RXD and out through RXDO while the TXD line is use...

Page 624: ...nsferred to the transmit shift register and a 1 is loaded to the 9th bit position as in mode 0 At phase 1 of the machine cycle after the next rollover in the divide by 16 counter the start bit is copi...

Page 625: ...omotive Applications UART1 UART2 Figure 163 Serial Interface Mode 1 Timing Diagram D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Stop Bit TXD TX Clock txd_en lin_rx _rdy SEND Data Shift TI D0 D1 D2 D3 D4 D5 D6 D7...

Page 626: ...n the TB8 bit gets to the output position the control block executes one last shift and sets the TI bit Reception is started by a high to low transition on RXD sampled at 16 times of the baud rate The...

Page 627: ...lications UART1 UART2 Figure 164 Serial Interface Modes 2 and 3 Timing Diagram D0 D1 D2 D3 D4 D5 D6 TB8 Start Bit Stop Bit TXD TX Clock txd_en lin_rx _rdy SEND Data Shift TI D0 D1 D2 D3 D4 D5 D6 RB8 S...

Page 628: ...rs from a data byte in the 9th bit The 9th bit in an address byte is 1 and in a data byte the 9th bit is 0 With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt...

Page 629: ...nput clock fsys The baud rate timer counts downwards and can be started or stopped through the baud rate control run bit BCON1 BR1_R Each underflow of the timer provides one clock pulse to the serial...

Page 630: ...tings and the deviation errors compared to the intended baud rate Table 332 Typical Baud Rates of UART fsys 40 MHz Baud rate fsys 40 MHz PRE Reload Value BR_VALUE Numerator of Fractional Value FD_SEL...

Page 631: ...without a crystal or ceramic resonator which significantly reduces the cost of hardware platform Hence the baud rate must be calculated and returned with every message frame The structure of a LIN fr...

Page 632: ...lave determines whether to receive or transmit data or do nothing 5 When transmitting the slave sends 2 4 or 8 data bytes followed by a Check Byte 19 7 2 LIN Header Transmission LIN header transmissio...

Page 633: ...hin the LIN protocol using Timer 2 Timer 21 Initialization consists of Setting of the serial port of the microcontroller to Mode 1 8 bit UART variable baud rate for communication Providing the baud ra...

Page 634: ...n the range of 9 2 kHz to 18 3 kHz selected BGSEL value is 01B If the baud rate falls in the range of 18 3 kHz to 555 6 kHz selected BGSEL value is 00B If the baud rate is 20 kHz the possible values o...

Page 635: ...eld flag LINST BRK is set software may continue to capture 4 6 8 bits of sync byte Finally the end of sync byte flag LINST EOFSYN is set Timer 2 is stopped T2 Reload Capture register RC is the time ta...

Page 636: ...the serial port interrupt bits TI and RI SBUF is the receive and transmit buffer of the serial interface Writing to SBUF loads the transmit register and initiates transmission This register is used fo...

Page 637: ...Offset Reset Value Serial Data Buffer 04H see Table 337 Field Bits Type Description RES 31 8 r Reserved Returns 0 if read should be written with 0 VAL 7 0 rwh Serial Interface Buffer Register Table 33...

Page 638: ...not be activated if the received 9th data bit RB8 is 0 Mode 1 if SM2 1 RI will not be activated if no valid stop bit RB8 was received Mode 0 SM2 should be 0 REN 4 rw Enable Receiver of Serial Port 0B...

Page 639: ...odes 1 2 and 3 Must be cleared by flag SCONCLR TICLR This flag can also be set by software RI 0 rw Receive Interrupt Flag This is set by hardware at the end of the 8th bit on mode 0 oratthehalfpointof...

Page 640: ...gure below sketches the structure of the complete UART LIN support hardware UART_SCONCLR Offset Reset Value Serial Channel Control Clear Register 08H see Table 339 Field Bits Type Description RES 31 3...

Page 641: ...ces to clock data in and out In modes 1 2 and 3 the port behaves as a UART Data is transmitted on TXD and received on RXD Data that is shifted into and out of the UART through RXD and TXD respectively...

Page 642: ...igure 172 UART2 Module I O Interface SCU_DM UART2 disreq from SCU_DM UART Module Kernel RI2 TI2 Clock Control Address Decoder fUART2 SCU_D M Interrupt Control SSCModule AHB Interface RXD_1 TXD_1 PortC...

Page 643: ...ash Mode 115 kbit s 250 kbit s Wake Up Features LIN Bus wake up The wake up happens on the falling edge of the LIN signal to allow wake up and decoding of the same frame It is possible to enter the sl...

Page 644: ...with LIN and Power Switches for Automotive Applications LIN Transceiver Mode can be used for data transfer under special conditions for up to 250 kbit s in production environment point to point commu...

Page 645: ...kBaud Fast Slope Mode for a transmission up to 40 kBaud Flash Mode for a transmission up to 115 kBaud 20 3 1 LIN Normal Mode The LIN Module is controlled by an internal state machine which determines...

Page 646: ...an be directly selected by application software or is automatically set upon error detection LIN Sleep Mode LSLM In this mode the transmit and receive functions are disabled the wake receiver is activ...

Page 647: ...and LIN_CTRL OC_IS are not set and no LIN_CTRL TXD_TMOUT is set and LNM LSLM transition is executed when LIN_CTRL MODE is configured LIN Sleep Mode LIN Normal Mode LNM LIN Receive Only Mode LROM Tran...

Page 648: ...TxD pin caused by a failure The failure is stored in the TXD_TMOUT flag The transmitter stage is activated again after the dominant timeout condition is removed and after the TXD_TMOUT flag is cleare...

Page 649: ...ing in LIN Normal Mode to avoid transmission errors To change the slope mode for example from Normal Slope Mode to Flash Mode it is necessary to change to LIN Receive Only Mode or LIN Sleep Mode confi...

Page 650: ...sibility to monitor the on chip status of the slope control through internally generated feedback signals The table shows the decoding of the feedback signals Table 341 Slope Mode Status LIN_FB_SM3 LI...

Page 651: ...FH Table 343 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition LIN_CTRL LIN Transceiver Control 00H 0000 0000 0001 1000 xxx0 0x10 0000 0111B LIN_I...

Page 652: ...al 1 for Slope Mode Setting Coding see Table 341 SM 12 11 rw LIN Transmitter Slope mode control 00B Normal Slope Mode for max 20 kBaud 01B Fast Slope Mode for max 40 kBaud 10B Low Slope Mode for max 1...

Page 653: ...RES 31 12 r Reserved Always read as 0 TXD_TMOUT_ STS 11 r LIN TXD time out Status 0B NO_TIMEOUT no time out occurred 1B TIMEOUT time out occurred RES 10 r Reserved Always read as 0 OT_STS 9 r LIN Rece...

Page 654: ...RR_I S 3 r LIN Transceiver Mode Error Slope Mode Error Interrupt Status 0B no Mode Error Slope Mode status occurred 1B Mode Error status occurred RES 2 0 r Reserved Always read as 1 Table 345 RESET of...

Page 655: ...O_Clear no time out cleared 1B Clear time out cleared OC_ISC 5 w LIN Receiver Overcurrent Interrupt Status Clear 0B NO_Clear overcurrent status not cleared 1B Clear overcurrent status cleared OT_ISC 4...

Page 656: ...efeedbackcontrolsignalsofLINTransceiverarenot correct Field Bits Type Description RES 31 7 r Reserved Always read as 0 TXD_TMOUT_ IEN 6 rw LIN Transceiver TxD Timeout interrupt enable 0B disable 1B en...

Page 657: ...al to Node 10 look like Figure 175 LIN Interrupt Signal Generation 1 0 0 0 0 0 Node 10 LIN_IRQEN OC_IEN LIN_IRQEN OT_IEN LIN _IRQS OC_IS LIN _IRQCLR OC_ISC LIN_IRQS OT_IS LIN_IRQCLR OT_ISC LIN OC LIN...

Page 658: ...condition On an error condition receive phase baud rate transmit error On a transfer complete condition Port direction selection see Chapter 15 21 2 Introduction The High Speed Synchronous Serial Int...

Page 659: ...eparate serial clock signal The SSC can be configured in a very flexible way so it can be used with other synchronous serial interfaces can serve for master slave or multimaster interconnections or ca...

Page 660: ...an active shift clock When the transfer starts the busy flag CON BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register TB may be reloaded again When the p...

Page 661: ...s transmitted first the transfer data is always right aligned in registers TB and RB with the LSB ofthe transfer data in bit 0 of these registers Thedata bits are rearranged for transfer by the intern...

Page 662: ...he respective port lines Figure 179 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in the configuration shown in Figure 1...

Page 663: ...laves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After th...

Page 664: ...n MRST for a master device MTSR for a slave By this method any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data Figure 180 SSC Half D...

Page 665: ...allows for each of the three SSC communication lines to be connected to two inputs coming from different port pins Operation of the SSC I O lines depends on the selected operating mode master or slave...

Page 666: ...written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baud rate 2...

Page 667: ...his allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent repeat...

Page 668: ...communication is stopped This is the case due to the fact that the SSC module supports back to back transfers for multiple transfers In order to handle this thebaudratedetectorexpectsafterafinished tr...

Page 669: ...smit buffer can be reloaded with new data Transmission ends RIR The configured number of bits have been transmitted and shifted to the receive buffer Receive Error EIR This interrupt occurs if a new d...

Page 670: ...48024000H 48025FFFH Synchronous Serial Interface 1 SSC2 48026000H 48027FFFH Synchronous Serial Interface 2 Table 351 Register Overview Register Short Name Register Long Name Offset Address Reset Valu...

Page 671: ...de only 0B Default Inputs selected according to MIS_0 1B Do not use Connects to unused pins CIS 2 rw Clock Input Select Slave Mode only 0B SSCx_S_SCK x 1 or 2 dependant form current SSC see Chapter 15...

Page 672: ...en EN 0 programming mode 0B NO error 1B ERROR More than factor 2 or 0 5 between slave s actual and expected baud rate PE 26 r Phase Error Flag Can only be read when EN 1 operating mode Invalid data wh...

Page 673: ...de Transmission and reception disabled Access to control bits 1B Operating Mode Transmission and reception enabled Access to status flags and M S control MS 14 rw Master Select 0B SLAVE Mode Operate o...

Page 674: ...alid data when EN 1 operating mode 0B LOW Idle clock line is low leading clock edge is low to high transition 1B HIGH Idle clock line is high leading clock edge is high to low transition PH 5 rw Clock...

Page 675: ...erved Returns 0 if read should be written with 0 BECLR 11 w Baud Rate Error Flag Clear 0B NO No error clear 1B CLEAR Error clear PECLR 10 w Phase Error Flag Clear 0B NO No error clear 1B CLEAR Error c...

Page 676: ...1 16 r Reserved Returns 0 if read should be written with 0 BR_VALUE 15 0 rw Baud Rate Timer Reload Register Value Reading BR returns the 16 bit contents of the baud rate timer Writing BR loads the bau...

Page 677: ...fer register RB contains the receive data value SSC_TB Offset Reset Value Transmitter Buffer Register 08H Table 356 Field Bits Type Description RES 31 16 r Reserved Returns 0 if read should be written...

Page 678: ...C1 or from SSC2 Please use the bits SSC_ in register SCU_MODPISEL for this purpose Field Bits Type Description RES 31 16 r Reserved Returns 0 if read should be written with 0 RB_VALUE 15 0 r Receive D...

Page 679: ...e is shown in the following figure Table 358 Measurement functions and associated modules Module Name Modules Functions Central Functions Unit Bandgap reference circuit current reference circuit The b...

Page 680: ...ress Note MF 48018000H 4801BFFFH Measurement Unit Measurement Unit 8 Bit ADC DPP 10 Bit ADC DPP MUX CH5 CH4 CH3 CH2 CH6 A D VS MUX CH2 CH1 CH0 VREF A D DPP1 10 8 DPP2 VBG SFR SFR ADC 1 ADC 2 PMU Bandg...

Page 681: ...ion time 15 system clock cycles programmable sampling time 4 to 22 MI_CLK cycles default 12 Scalable clock frequency from 10 30 MHz The next chapter shows the channel allocation of the 8 Bit ADC Core...

Page 682: ...of both A D converters is given in Chapter Electrical Characteristics The Gain for each channel can be found in the table included in the following chapter 22 3 3 Detailed ADC2 Measurement Channel Des...

Page 683: ...rement VBAT_SENSE Pin Voltage Measurement MON1 5 Pin Voltage Measurement P2 x Pin Voltage Measurement Table 361 ADC1 Channel Selection and Voltage Ranges Channel Measurement Input Pin Gain of channel...

Page 684: ...tions Measurement Unit 7 vsense_p21_ai 56 256 5 53 8 vsense_p22_ai 56 256 5 53 9 vsense_p23_ai 56 256 5 53 10 vsense_p26_ai 56 256 5 53 11 vsense_p27_ai 56 256 5 53 12 vsense_p20_ai 56 256 5 53 Table...

Page 685: ...s the chip temperature and PMU Regulator temperature One sensing element is placed in the centre of the device to get the average device temperature status and the other sensing element is close to th...

Page 686: ...errupt status set SYS_OTWARN_STS 6 r System Overtemperature Warning MU Status 0B INACTIVE write clears status 1B ACTIVE interrupt status set LS_OT_STS 5 r Low Side Overtemperature MU Status 0B INACTIV...

Page 687: ...guration possibilities of the on chip references 22 6 1 Functional Safety Concept 8 bit ADC Module 2 A known voltage e g reference voltage of the main supply module is periodically measured as part of...

Page 688: ...eference 1 Status Register 14H 0000 00C1H MF_REF1_STS Offset Reset Value Reference 1 Status Register 14H see Table 365 Field Bits Type Description RES 31 10 r Reserved Always read as 0 RES 9 6 r Reser...

Page 689: ...8 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Measurement Unit Table 365 RESET of MF_REF1_STS Register Reset Type Reset Values Reset Short Name Reset Mode Note RE...

Page 690: ...and lower trigger thresholds comprising a fully programmable hysteresis Two individually programmable trigger thresholds with limit hysteresis settings Individually programmable interrupts and status...

Page 691: ...an be controlled in a flexible way which allows a certain degree of channel prioritization This capability can be used e g to set a higher priority to supply voltage channels compared to the other cha...

Page 692: ...S The Software Mode is left when the maximum time is reached maximum time specified in ADC2_MAX_TIME or when the sequence which started the software mode is reprogrammed with at least one channel set...

Page 693: ...enable the sequencer again this corresponding bits in the sequencer register must be set to one again Table 366 shows the module base addresses The registers are addressed wordwise Table 366 Register...

Page 694: ...le 0011B CH3_EN Channel 3 enable 0100B CH4_EN Channel 4 enable 0101B CH5_EN Channel 5 enable 0110B CH6_EN Channel 6 enable 0111B rfu reserved for future use 1xxxB rfu reserved for future use RES 7 4 r...

Page 695: ...r Automotive Applications Measurement Core Module incl ADC2 RES 1 r Reserved Always read as 0 RES 0 r Reserved Always read as 0 Table 368 RESET of ADC2_CTRL_STS Register Reset Type Reset Values Reset...

Page 696: ...e Table 369 Field Bits Type Description RES 31 2 r Reserved Always read as 0 READY 1 r HVADC Ready bit 0B Not ready Module in power down or in init phase 1B Ready set automatically 5 ADC clock cycles...

Page 697: ...nnel sequence is defined as CH5 CH4 CH2 CH1 CH0 CH6 CH3 CH5 CH4 CH2 CH1 CH5 CH4 CH2 CH1 CH0 In TLE984xQX Channels 0 6 can not be programmed by the user All Sequence registers especially for high prior...

Page 698: ...nts of the internal circuits e g shutdown in case of overtemperature for the low sides and protection overtemperature protection of the system The minimum measurement periodicity which can be achieved...

Page 699: ...1 Register Overview Register Short Name Register Long Name Offset Address Reset Value Channel Controller Control Registers ADC2_SQ_FB Sequencer Feedback Register 04H 0000 0000 000X XXXX 0XXX XXXX 0000...

Page 700: ...erved Always read as 0 CALIB_EN_6_0 6 0 rwpt Calibration Enable for Channels 6 to 0 The following values can be ored 000 0001BCH0_EN Channel 0 calibration enable 000 0010BCH1_EN Channel 1 calibration...

Page 701: ...lock periods AH n u not used BH n u not used CH n u not used DH n u not used EH n u not used FH n u not used MCM_RDY 7 r Ready Signal for MCM1 after Power On or Reset 0B MCM Not Ready Measurement Core...

Page 702: ...er 000 0010BChannel 1 IIR Data enabled for ADC2_FILT_OUT1 Register 000 0100BChannel 2 IIR Data enabled for ADC2_FILT_OUT2 Register 000 1000BChannel 3 IIR Data enabled for ADC2_FILT_OUT3 Register 001 0...

Page 703: ...t Sequence 3 channel enable The following values can be ored 000 0001BCH0_EN Channel 0 enable 000 0010BCH1_EN Channel 1 enable 000 0100BCH2_EN Channel 2 enable 000 1000BCH3_EN Channel 3 enable 001 000...

Page 704: ...ues can be ored 000 0001BCH0_EN Channel 0 enable 000 0010BCH1_EN Channel 1 enable 000 0100BCH2_EN Channel 2 enable 000 1000BCH3_EN Channel 3 enable 001 0000BCH4_EN Channel 4 enable 010 0000BCH5_EN Cha...

Page 705: ...0 enable 000 0010BCH1_EN Channel 1 enable 000 0100BCH2_EN Channel 2 enable 000 1000BCH3_EN Channel 3 enable 001 0000BCH4_EN Channel 4 enable 010 0000BCH5_EN Channel 5 enable 100 0000BCH6_EN Channel 6...

Page 706: ...ues can be ored 000 0001BCH0_EN Channel 0 enable 000 0010BCH1_EN Channel 1 enable 000 0100BCH2_EN Channel 2 enable 000 1000BCH3_EN Channel 3 enable 001 0000BCH4_EN Channel 4 enable 010 0000BCH5_EN Cha...

Page 707: ...el 2 enable 0011B CH3 Channel 3 enable 0100B CH4 Channel 4 enable 0101B CH5 Channel 5 enable 0110B CH6 Channel 6 enable RES 15 14 r Reserved Always read as 0 SQx_STS 13 11 r Current Active ADC2 Sequen...

Page 708: ...ad as 0 SQ_FB 3 0 r Current Sequence that caused software mode Other bit combinations are n u not used 0000B SQ1 Sequence 1 0001B SQ2 Sequence 2 0010B SQ3 Sequence 3 0011B SQ4 Sequence 4 0100B SQ5 Seq...

Page 709: ...surement EIM Trigger select Always read as 0 0B GPT12PISEL T3_GPT12_SEL GPT12_PISEL triggers EIM 1B not supported EN 11 rw Exceptional interrupt measurement EIM Trigger Event enable Always read as 0 0...

Page 710: ...combinations are n u not used 000B CH0_EN Channel 0 enable 001B CH1_EN Channel 1 enable 010B CH2_EN Channel 2 enable 011B CH3_EN Channel 3 enable 100B CH4_EN Channel 4 enable 101B CH5_EN Channel 5 en...

Page 711: ...d Bits Type Description RES 31 8 r Reserved Always read as 0 MAX_TIME 7 0 rw Maximum Time in Software Mode Maximum time in Software Mode with the unit of 50 ns Software mode is active for ADC2_MAX_TIM...

Page 712: ...ain Error of Reference Voltage All these factors are summed up in the overall Gain factor b and overall Offset adder a of the complete measurement chain They are calculated from a two point test resul...

Page 713: ...IN and Power Switches for Automotive Applications Measurement Core Module incl ADC2 Figure 188 Structure of Calibration Unit 0 1 Calibration Unit y a 1 b x b 7 0 a 7 0 CALIB_EN 8 8 8 10 10 ALU 16 Bit...

Page 714: ...ers ADC2_CAL_CH0_1 Calibration for Channel 0 1 34H 0000 0000H ADC2_CAL_CH2_3 Calibration for Channel 2 3 38H 0000 0000H ADC2_CAL_CH4_5 Calibration for Channel 4 5 3CH 0000 0000H ADC2_CAL_CH6_7 Calibra...

Page 715: ...Bits Type Description GAIN_CH3 31 24 rwpt Gain Calibration for channel 3 For ADC output set CALIB_EN_3 0 RES 23 21 r Reserved Always read as 0 OFFS_CH3 20 16 rwpt Offset Calibration for channel 3 For...

Page 716: ...eserved Always read as 0 OFFS_CH5 20 16 rwpt Offset Calibration for channel 5 For ADC output set CALIB_EN_5 0 GAIN_CH4 15 8 rwpt Gain Calibration for channel 4 For ADC output set CALIB_EN_4 0 RES 7 5...

Page 717: ...read as 0 GAIN_CH6 15 8 rwpt Gain Calibration for channel 6 For ADC output set CALIB_EN_6 0 RES 7 5 r Reserved Always read as 0 OFFS_CH6 4 0 rwpt Offset Calibration for channel 6 For ADC output set C...

Page 718: ...shown in the picture below Figure 189 IIR Filter Implementation Structure 23 5 This filter allows an effective suppression of high frequency components like noise or crosstalk caused by HF components...

Page 719: ...Step Response The IIR filter s step response time is shown in the figure below Figure 191 IIR Step Response Time Table 385 summarizes the main filter characteristics 0 1 2 3 4 5 6 x 10 4 80 60 40 20 0...

Page 720: ...03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Measurement Core Module incl ADC2 Table 385 IIR filter characteristics Filter coefficient Group delay at 0 a sam...

Page 721: ...or the calculated values in the ADC2_FILT_OUT0 to ADC2_FILT_OUT6 registers and gets access to 10 bit wide result information Table 386 ADC2_FILT_OUT Register Setting ADC2_CTRL1 calib_en ADC2_CTRL4 fil...

Page 722: ...RES 31 16 r Reserved Always read as 0 A_CH7 15 14 rwpt Filter Coefficient A for ADC channel 7 Note this bits are dedicated for future use They are always read as 0 00B 1 2 weight of current sample 01B...

Page 723: ...weight of current sample 10B 1 8 weight of current sample 11B 1 16 weight of current sample A_CH2 5 4 rwpt Filter Coefficient A for ADC channel 2 00B 1 2 weight of current sample 01B 1 4 weight of cu...

Page 724: ...Value ADC or Filter Output Channel 0 50H see Table 389 Field Bits Type Description RES 31 10 r Reserved Always read as 0 OUT_CH0 9 0 r ADC or filter output value channel 0 For ADC output set ADC2_FILT...

Page 725: ...Field Bits Type Description RES 31 10 r Reserved Always read as 0 OUT_CH1 9 0 r ADC or filter output value channel 1 For ADC output set ADC2_FILTUP_1_EN 0 Table 390 RESET of ADC2_FILT_OUT1 Register Re...

Page 726: ...its Type Description RES 31 10 r Reserved Always read as 0 OUT_CH2 9 0 r ADC or filter output value channel 2 For ADC output set ADC2_FILTUP_2_EN 0 Table 391 RESET of ADC2_FILT_OUT2 Register Reset Typ...

Page 727: ...Field Bits Type Description RES 31 10 r Reserved Always read as 0 OUT_CH3 9 0 r ADC or filter output value channel 3 For ADC output set ADC2_FILTUP_3_EN 0 Table 392 RESET of ADC2_FILT_OUT3 Register Re...

Page 728: ...its Type Description RES 31 10 r Reserved Always read as 0 OUT_CH4 9 0 r ADC or filter output value channel 4 For ADC output set ADC2_FILTUP_4_EN 0 Table 393 RESET of ADC2_FILT_OUT4 Register Reset Typ...

Page 729: ...s Reset Short Name Reset Mode Note RESET_TYPE_3 00000XXXH RESET_TYPE_3 Exact Reset Value 0000 0000 0000 0000 0000 00XX XXXX XXXX B ADC2_FILT_OUT6 Offset Reset Value ADC or Filter Output Channel 6 68H...

Page 730: ...1 the inverted lower comparator output signal STH_LO_CHX is normalized again When the output signal is above TH_LO_CHX the lower counter is incremented until the max threshold 2CNT_LO_CHX is reached I...

Page 731: ..._OV UV 1 can be used as prewarning for the application software e g close to overtemperature or supply undervoltage ADC_OUT VBAT overvoltage detection undervoltage detection a MMODE_OV UV 0 range cont...

Page 732: ...CTRL Lower Threshold Filter Enable 7CH 0000 007FH ADC2_TH0_3_LOWER Lower Comparator Trigger Level Channel 0 3 80H 9D6F BF25H ADC2_TH4_7_LOWER Lower Comparator Trigger Level Channel 4 7 84H 00C8 D4D4H...

Page 733: ...ble 1B enable UPEN_Ch4 4 rw Upper threshold IIR filter enable ch 4 0B disable 1B enable UPEN_Ch3 3 rw Upper threshold IIR filter enable ch 3 0B disable 1B enable UPEN_Ch2 2 rw Upper threshold IIR filt...

Page 734: ...eserved Always read as 0 LOEN_Ch6 6 rw Lower threshold IIR filter enable ch 6 0B disable 1B enable LOEN_Ch5 5 rw Lower threshold IIR filter enable ch 5 0B disable 1B enable LOEN_Ch4 4 rw Lower thresho...

Page 735: ...ervoltage limit measurement 10B MMODEOV overvoltage limit measurement 11B RESERVED reserved MSEL_Ch6 13 12 rwpt Measurement mode ch 6 00B MMODE0 upper lower voltage limit measurement 01B MMODEUV under...

Page 736: ...ndervoltage limit measurement 10B MMODEOV overvoltage limit measurement 11B RESERVED reserved MSEL_Ch1 3 2 rwpt Measurement mode ch 1 00B MMODE0 upper lower voltage limit measurement 01B MMODEUV under...

Page 737: ...l 00H min threshold value 0 FFH max threshold value 255 THUP_CH2 23 16 rw Channel 2 upper trigger level 00H min threshold value 0 FFH max threshold value 255 THUP_CH1 15 8 rw Channel 1 upper trigger l...

Page 738: ...use They are always read as 0 00H min threshold value 0 FFH max threshold value 255 THUP_CH6 23 16 rwpt Channel 6 upper trigger level 00H min threshold value 0 FFH max threshold value 255 THUP_CH5 15...

Page 739: ...4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_CH3 26 24 rw Upper timer trigger threshold channel 3 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5...

Page 740: ...H1 10 8 rw Upper timer trigger threshold channel 1 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements RE...

Page 741: ...sis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_CH7 26 24 rw Upper timer trigger threshold channel 7 Note this bits are dedicated for future use They are always read as 0 0H 1 measurement 1...

Page 742: ...H5 10 8 rw Upper timer trigger threshold channel 5 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements RE...

Page 743: ...ger level 00H Min threshold value FFH Max threshold value THLO_CH2 23 16 rwpt Channel 2 lower trigger level 00H Min threshold value FFH Max threshold value THLO_CH1 15 8 rw Channel 1 lower trigger lev...

Page 744: ...edicated for future use They are always read as 0 00H Min threshold value FFH Max threshold value THLO_CH6 23 16 rw Channel 6 lower trigger level 00H Min threshold value FFH Max threshold value THLO_C...

Page 745: ...4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH3 26 24 rw Lower timer trigger threshold channel 3 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5...

Page 746: ...T4 hysteresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH1 10 8 rw Lower timer trigger threshold channel 1 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 me...

Page 747: ...Microcontroller with LIN and Power Switches for Automotive Applications Measurement Core Module incl ADC2 Table 406 RESET of ADC2_CNT0_3_LOWER Register Reset Type Reset Values Reset Short Name Reset M...

Page 748: ...hey are always read as 0 0H HYSTOFF hysteresis switched off 1H HYST4 hysteresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH7 26 24 rw Lower timer trigger threshold channel 6 Note this bi...

Page 749: ...measurements 6H 63 measurements 7H 63 measurements RES 15 13 r Reserved Always read as 0 HYST_LO_CH5 12 11 rw Channel 5 lower hysteresis 0H HYSTOFF hysteresis switched off 1H HYST4 hysteresis 4 2H HYS...

Page 750: ...2 0 rw Lower timer trigger threshold channel 4 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements Table...

Page 751: ...during power up Since the channels 6 9 of the unit are exclusively used for internal measurements they can only be partly accessed by the application software Table 408 Channel allocation and postpro...

Page 752: ...2 2 P2 3 P2 6 P2 7 P2 0 One additional channel ch12 connected to P2 0 product variant dependant This channel is only programmable in software mode no calibration and no digital postprocessing are avai...

Page 753: ...a higher priority to supply voltage channels compared to the other channel measurements The Measurement Core Module offers additionally two different post processing measurement modes for over undervo...

Page 754: ...Rev 1 1 2019 03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 The threshold counter can be bypassed ADC1_FILT_UP_CTRL and AD...

Page 755: ...During Software Mode EIM and ESM hardware events are ignored Software Mode Software mode can be entered in different ways by writing one of the sequence registers SQn e g to SQ1 11 0 to zero or setti...

Page 756: ...cer Once the Debug Suspend Mode is left the Sequencer continues immediately with the next pending measurement Measurements can be still triggered in Debug Suspend Mode Software Mode The maximum time o...

Page 757: ...Value ADC1 Control and Status Register 00H see Table 411 Field Bits Type Description RES 31 19 r Reserved Always read as 0 STRTUP_DIS 18 rw DPP1 Startup Disable 0B Startup Enable DPP1 Startup enabled...

Page 758: ...0110B CH6_EN Channel 6 enable 0111B CH7_EN Channel 7 enable 1000B CH8_EN Channel 8 enable 1001B CH9_EN Channel 9 enable 1010B CH10_EN Channel 10 enable 1011B CH11_EN Channel 11 enable 1100B CH12_EN Ch...

Page 759: ...s cleared by hardware once the conversion is finished ADC1_SOS can be only written if the DPP is in software mode 0B Disable no conversion is started 1B Enable conversion is started RES 1 rwh1 Reserve...

Page 760: ...nt sequence will be continued with the next measurement from the current sequence Exceptional Sequence Measurement ESM upon hardware event the sequence programmed in ADC1_CHx_ESM is inserted after the...

Page 761: ...quence is defined as CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH5 CH4 CH3 CH2 CH11 CH11 In TLE984xQX Channels 0 11 can be fully programmed The channels 0 11 are measured depending on the amount of 1 bits...

Page 762: ...rement value is 17 clock cycles The minimum measurement periodicity which can be achieved by enabling only channel 1 in the sequence registers depends on the ADC1_CLK frequency and is given by This fo...

Page 763: ...Bits for Exceptional Sequence Measurement 0CH 0000 0000H ADC1_MAX_TIME Maximum Time for Software Mode 10H 0000 0000H ADC1_CTRL2 Measurement Unit 1 Control Register 2 14H 0000 0000H ADC1_CTRL3 Measure...

Page 764: ...can be ored 0000 0000 0001BCH0_EN Channel 0 calibration enable 0000 0000 0010BCH1_EN Channel 1 calibration enable 0000 0000 0100BCH2_EN Channel 2 calibration enable 0000 0000 1000BCH3_EN Channel 3 ca...

Page 765: ...lock periods default 1H MICLK6 6 ADC1_CLK clock periods 2H MICLK8 8 ADC1_CLK clock periods 3H MICLK10 10 ADC1_CLK clock periods 4H MICLK12 12 ADC1_CLK clock periods 5H MICLK14 14 ADC1_CLK clock period...

Page 766: ...MICLK4 4 ADC1_CLK clock periods BH MICLK4 4 ADC1_CLK clock periods CH MICLK4 4 ADC1_CLK clock periods DH MICLK4 4 ADC1_CLK clock periods EH MICLK4 4 ADC1_CLK clock periods FH MICLK4 4 ADC1_CLK clock...

Page 767: ...onverter ADC1 MCM_PD_N 0 rw Power Down Signal for MCM 0B MCM Disabled Measurement Core Module Disabled 1B MCM Enabled Measurement Core Module Enabled 1 MCM Measurement Core Module Table 415 RESET of A...

Page 768: ...MAX_CALTIME 3 0 rw Maximum ADC Calibration Time Defines how often the ADC calibration is done within the sequencer cycle 0H 1 Sequence 1H 2 Sequences 2H 3 Sequences 3H 4 Sequences 4H 5 Sequence 5H 6...

Page 769: ...abled for FILT_OUT1 Register 0000 0000 0100BChannel 2 IIR Data enabled for FILT_OUT2 Register 0000 0000 1000BChannel 3 IIR Data enabled for FILT_OUT3 Register 0000 0001 0000BChannel 4 IIR Data enabled...

Page 770: ...X Microcontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 417 RESET of ADC1_CTRL5 Register Reset Type Reset Values Reset Short Name Reset Mod...

Page 771: ...nel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable...

Page 772: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 773: ...nel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable...

Page 774: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 775: ...nel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable...

Page 776: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 777: ...nel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable...

Page 778: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 779: ...nel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable...

Page 780: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 781: ...hannel enable The following values can be ored 0000 0000 0001BCH0_EN Channel 0 enable 0000 0000 0010BCH1_EN Channel 1 enable 0000 0000 0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enab...

Page 782: ...nel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000BCH7_EN Channel 7...

Page 783: ...t ADC1 Channel Other bit combinations are reserved do not use 0000B CH0 Channel 0 enable 0001B CH1 Channel 1 enable 0010B CH2 Channel 2 enable 0011B CH3 Channel 3 enable 0100B CH4 Channel 4 enable 010...

Page 784: ...1B SQ11 Sequence 11 enable ESM_ACTIVE 10 r ADC1 ESM active Note this bit indicates an active or a pending sequence measurement a pending measurement is signalled when EIM or Software Mode is selected...

Page 785: ...e 0 0100B SQ4 Sequence 4 enable 0 0101B SQ5 Sequence 5 enable 0 0110B SQ6 Sequence 6 enable 0 0111B SQ7 Sequence 7 enable 0 1000B SQ8 Sequence 8 enable 0 1001B SQ9 Sequence 9 enable 0 1010B SQ10 Seque...

Page 786: ...T63 010B GPT12_T6OUT 011B GPT12_T3OUT 100B T2 t2_adc_trigger 101B T21 t21_adc_trigger 110B RES reserved 111B RES reserved RES 15 12 r Reserved Always read as 0 EIM_EN 11 rw Exceptional interrupt measu...

Page 787: ...Channel 0 enable 0001B CH1_EN Channel 1 enable 0010B CH2_EN Channel 2 enable 0011B CH3_EN Channel 3 enable 0100B CH4_EN Channel 4 enable 0101B CH5_EN Channel 5 enable 0110B CH6_EN Channel 6 enable 01...

Page 788: ...r ESM interrupts can be triggered 0B not active Exceptional Sequence Measurement not done 1B done Exceptional Sequence Measurement done ESM_EN 30 rw Enable for Exceptional Sequence Measurement Trigger...

Page 789: ...0100BCH2_EN Channel 2 enable 0000 0000 1000BCH3_EN Channel 3 enable 0000 0001 0000BCH4_EN Channel 4 enable 0000 0010 0000BCH5_EN Channel 5 enable 0000 0100 0000BCH6_EN Channel 6 enable 0000 1000 0000B...

Page 790: ...ld Bits Type Description RES 31 8 r Reserved Always read as 0 MAX_TIME 7 0 rw Maximum Time in Software Mode Maximum time in Software Mode with the unit of 50 ns Software mode is active for ADC1_MAX_TI...

Page 791: ...factors are summed up in the overall Gain factor b and overall Offset adder a of the complete measurement chain They are calculated from a two point test result and stored inside the NVM Note The cali...

Page 792: ...r with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Figure 196 Structure of Calibration Unit 0 1 Calibration Unit y a 1 b x b a CALIB_EN 10 10 10 12 12 ALU 2...

Page 793: ...for Channel 0 1 48H 0000 0000H ADC1_CAL_CH2_3 Calibration for Channel 2 3 4CH 0000 0000H ADC1_CAL_CH4_5 Calibration for Channel 4 5 50H 0000 0000H ADC1_CAL_CH6_7 Calibration for Channel 6 7 54H 0000 0...

Page 794: ...Bit Analog Digital Converter ADC1 RES 7 5 r Reserved Always read as 0 CALOFFS_CH0 4 0 rw Offset Calibration for channel 0 For ADC output set CALIB_EN_0 0 Table 429 RESET of ADC1_CAL_CH0_1 Register Re...

Page 795: ...CALIB_EN_3 0 RES 23 21 r Reserved Always read as 0 CALOFFS_CH3 20 16 rw Offset Calibration for channel 3 For ADC output set CALIB_EN_3 0 CALGAIN_CH2 15 8 rw Gain Calibration for channel 2 For ADC outp...

Page 796: ...CALIB_EN_5 0 RES 23 21 r Reserved Always read as 0 CALOFFS_CH5 20 16 rw Offset Calibration for channel 5 For ADC output set CALIB_EN_5 0 CALGAIN_CH4 15 8 rw Gain Calibration for channel 4 For ADC outp...

Page 797: ...CALIB_EN_7 0 RES 23 21 r Reserved Always read as 0 CALOFFS_CH7 20 16 rw Offset Calibration for channel 7 For ADC output set CALIB_EN_7 0 CALGAIN_CH6 15 8 rw Gain Calibration for channel 6 For ADC outp...

Page 798: ...CALIB_EN_9 0 RES 23 21 r Reserved Always read as 0 CALOFFS_CH9 20 16 rw Offset Calibration for channel 9 For ADC output set CALIB_EN_9 0 CALGAIN_CH8 15 8 rw Gain Calibration for channel 8 For ADC outp...

Page 799: ...B_EN_11 0 RES 23 21 r Reserved Always read as 0 CALOFFS_CH11 20 16 rw Offset Calibration for channel 11 For ADC output set CALIB_EN_11 0 CALGAIN_CH10 15 8 rw Gain Calibration for channel 10 For ADC ou...

Page 800: ...rst order IIR Filter The structure of the IIR Filter is shown in the picture below Figure 197 IIR Filter Implementation Structure 24 5 This filter allows an effective suppression of high frequency com...

Page 801: ...g frequency 24 7 1 1 Step Response The IIR filter s step response time is shown in the figure below Figure 199 IIR Step Response Time HIIR z 1 a z 1 1 a 0 1 2 3 4 5 6 x 10 4 80 60 40 20 0 Frequency Hz...

Page 802: ...r ADC1 Table 435 summarizes the main filter characteristics Table 435 IIR filter characteristics Filter coefficient Group delay at 0 Normalized 3dB frequency 1 1 The filter s 3dB frequency is normaliz...

Page 803: ...T0 to ADC1_FILT_OUT11 registers and gets access to 10 bit wide result information Table 436 ADC1_FILT_OUT register setting ADC1_CTRL2 calib_en ADC1_CTRL5 filt_out_sel ADC1_FILT_OUT0 output 1 0 0 0 00...

Page 804: ...or Filter Output Channel 9 94H 0000 0000 0000 0000 0000 00XX XXXX XXXXB ADC1_FILT_OUT10 ADC1 or Filter Output Channel 10 98H 0000 0000 0000 0000 0000 00XX XXXX XXXXB ADC1_FILT_OUT11 ADC1 or Filter Out...

Page 805: ...el 0 11 60H see Table 438 Field Bits Type Description RES 31 24 r Reserved Always read as 0 CH11 23 22 rw Filter Coefficients ADC channel 11 00B 1 2 weight of current sample 01B 1 4 weight of current...

Page 806: ...nt sample 10B 1 8 weight of current sample 11B 1 16 weight of current sample CH5 11 10 rw Filter Coefficients ADC channel 5 00B 1 2 weight of current sample 01B 1 4 weight of current sample 10B 1 8 we...

Page 807: ...DC1 CH0 1 0 rw Filter Coefficients ADC channel 0 00B 1 2 weight of current sample 01B 1 4 weight of current sample 10B 1 8 weight of current sample 11B 1 16 weight of current sample Table 438 RESET of...

Page 808: ...Only set in WFRx DISABLE and no software mode clear on read of FILT_OUT_CH0 register 0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF0 17 rh Valid Flag Indicate...

Page 809: ...15 12 r Reserved Always read as 0 FILT_OUT_CH0 11 0 r ADC or filter output value channel 0 For ADC output set ADC1_FILTUP_0_EN 0 Table 439 RESET of ADC1_FILT_OUT0 Register Reset Type Reset Values Rese...

Page 810: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF1 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH1 Note Bit is set by hardware...

Page 811: ...Converter ADC1 FILT_OUT_CH1 11 0 r ADC or filter output value channel 1 For ADC output set ADC1_FILTUP_1_EN 0 Table 440 RESET of ADC1_FILT_OUT1 Register Reset Type Reset Values Reset Short Name Reset...

Page 812: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF2 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH2 Note Bit is set by hardware...

Page 813: ...Converter ADC1 FILT_OUT_CH2 11 0 r ADC or filter output value channel 2 For ADC output set ADC1_FILTUP_2_EN 0 Table 441 RESET of ADC1_FILT_OUT2 Register Reset Type Reset Values Reset Short Name Reset...

Page 814: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF3 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH3 Note Bit is set by hardware...

Page 815: ...Converter ADC1 FILT_OUT_CH3 11 0 r ADC or filter output value channel 3 For ADC output set ADC1_FILTUP_3_EN 0 Table 442 RESET of ADC1_FILT_OUT3 Register Reset Type Reset Values Reset Short Name Reset...

Page 816: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF4 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH4 Note Bit is set by hardware...

Page 817: ...Converter ADC1 FILT_OUT_CH4 11 0 r ADC or filter output value channel 4 For ADC output set ADC1_FILTUP_4_EN 0 Table 443 RESET of ADC1_FILT_OUT4 Register Reset Type Reset Values Reset Short Name Reset...

Page 818: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF5 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH5 Note Bit is set by hardware...

Page 819: ...Converter ADC1 FILT_OUT_CH5 11 0 r ADC or filter output value channel 5 For ADC output set ADC1_FILTUP_5_EN 0 Table 444 RESET of ADC1_FILT_OUT5 Register Reset Type Reset Values Reset Short Name Reset...

Page 820: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF6 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH6 Note Bit is set by hardware...

Page 821: ...Converter ADC1 FILT_OUT_CH6 11 0 r ADC or filter output value channel 6 For ADC output set ADC1_FILTUP_6_EN 0 Table 445 RESET of ADC1_FILT_OUT6 Register Reset Type Reset Values Reset Short Name Reset...

Page 822: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF7 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH7 Note Bit is set by hardware...

Page 823: ...Converter ADC1 FILT_OUT_CH7 11 0 r ADC or filter output value channel 7 For ADC output set ADC1_FILTUP_7_EN 0 Table 446 RESET of ADC1_FILT_OUT7 Register Reset Type Reset Values Reset Short Name Reset...

Page 824: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF8 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH8 Note Bit is set by hardware...

Page 825: ...Converter ADC1 FILT_OUT_CH8 11 0 r ADC or filter output value channel 8 For ADC output set ADC1_FILTUP_8_EN 0 Table 447 RESET of ADC1_FILT_OUT8 Register Reset Type Reset Values Reset Short Name Reset...

Page 826: ...0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF9 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH9 Note Bit is set by hardware...

Page 827: ...Converter ADC1 FILT_OUT_CH9 11 0 r ADC or filter output value channel 9 For ADC output set ADC1_FILTUP_9_EN 0 Table 448 RESET of ADC1_FILT_OUT9 Register Reset Type Reset Values Reset Short Name Reset...

Page 828: ...NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF10 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH10 Note Bit is set by hardware...

Page 829: ...nverter ADC1 FILT_OUT_CH10 11 0 r ADC or filter output value channel 10 For ADC output set ADC1_FILTUP_10_EN 0 Table 449 RESET of ADC1_FILT_OUT10 Register Reset Type Reset Values Reset Short Name Rese...

Page 830: ...NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF11 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH11 Note Bit is set by hardware...

Page 831: ...nverter ADC1 FILT_OUT_CH11 11 0 r ADC or filter output value channel 11 For ADC output set ADC1_FILTUP_11_EN 0 Table 450 RESET of ADC1_FILT_OUT11 Register Reset Type Reset Values Reset Short Name Rese...

Page 832: ...B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten VF12 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_OUT_CH12 Note Bit is set by hardwar...

Page 833: ...nverter ADC1 FILT_OUT_CH12 11 0 r ADC or filter output value channel 12 For ADC output set ADC1_FILTUP_12_EN 0 Table 451 RESET of ADC1_FILT_OUT12 Register Reset Type Reset Values Reset Short Name Rese...

Page 834: ...set if VFx 1 and new result is updated by hardware Note Only set in WFRx DISABLE and no software mode clear on read of FILT_OUT_EIM register 0B NO OVERRUN Result register not overwritten 1B OVERRUN R...

Page 835: ...esult register 0B DISABLE overwrite mode 1B ENABLE wait for read mode enabled RES 15 12 r Reserved Always read as 0 FILT_OUT_EIM 11 0 r ADC or filter output value for last EIM measurement Table 452 RE...

Page 836: ...gister 0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten DVF1 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_DOUT1 Note Bit is set by ha...

Page 837: ...s 10 Bit Analog Digital Converter ADC1 DCH1 11 0 r ADC differential output value 1 Table 453 RESET of ADC1_DIFFCH_OUT1 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00...

Page 838: ...gister 0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten DVF2 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_DOUT2 Note Bit is set by ha...

Page 839: ...s 10 Bit Analog Digital Converter ADC1 DCH2 11 0 r ADC differential output value 2 Table 454 RESET of ADC1_DIFFCH_OUT2 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00...

Page 840: ...gister 0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten DVF3 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_DOUT3 Note Bit is set by ha...

Page 841: ...s 10 Bit Analog Digital Converter ADC1 DCH3 11 0 r ADC differential output value 3 Table 455 RESET of ADC1_DIFFCH_OUT3 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00...

Page 842: ...gister 0B NO OVERRUN Result register not overwritten 1B OVERRUN Result register overwritten DVF4 17 rh Valid Flag Indicates valid contents in result register bit field ADC1_DOUT4 Note Bit is set by ha...

Page 843: ...s 10 Bit Analog Digital Converter ADC1 DCH4 11 0 r ADC differential output value 4 Table 456 RESET of ADC1_DIFFCH_OUT4 Register Reset Type Reset Values Reset Short Name Reset Mode Note RESET_TYPE_3 00...

Page 844: ...verted lower comparator output signal STH_LO_CHX is normalized again When the output signal is above TH_LO_CHX the lower counter is incremented until the max threshold 2CNT_LO_CHX is reached Individua...

Page 845: ...modes MMODE_OV UV 1 can be used as prewarning for the application software e g close to supply undervoltage ADC_OUT VBAT overvoltage detection undervoltage detection a MMODE_OV UV 0 range control filt...

Page 846: ...ferential Channel 1 4 C4H 0000 0000H ADC1_TH0_3_UPPER Upper Comparator Trigger Level Channel 0 3 C8H AB8D C5C0H ADC1_TH4_7_UPPER Upper Comparator Trigger Level Channel 4 7 CCH 0000 0000H ADC1_TH8_11_U...

Page 847: ...er threshold IIR filter enable Channel 9 0B disable 1B enable FU_CH8_EN 8 rw Upper threshold IIR filter enable Channel 8 0B disable 1B enable FU_CH7_EN 7 rw Upper threshold IIR filter enable Channel 7...

Page 848: ...le 1B enable FU_CH2_EN 2 rw Upper threshold IIR filter enable Channel 2 0B disable 1B enable FU_CH1_EN 1 rw Upper threshold IIR filter enable Channel 1 0B disable 1B enable FU_CH0_EN 0 rw Upper thresh...

Page 849: ...Channel 10 0B disable 1B enable FL_CH9_EN 9 rw Lower threshold IIR filter enable Channel 9 0B disable 1B enable FL_CH8_EN 8 rw Lower threshold IIR filter enable Channel 8 0B disable 1B enable FL_CH7_E...

Page 850: ...4 ADC1_MMODE0_11 Offset Reset Value Overvoltage Measurement Mode of Ch 0 11 F8H see Table 460 Field Bits Type Description MMODE_D4 31 30 rw Measurement mode Differential Channel 4 00B MMODE0 upper low...

Page 851: ...it measurement 10B MMODEOV overvoltage limit measurement 11B RESERVED reserved MMODE_9 19 18 rw Measurement mode Channel 9 00B MMODE0 upper lower voltage limit measurement 01B MMODEUV undervoltage lim...

Page 852: ...E_2 5 4 rw Measurement mode Channel 2 00B MMODE0 upper lower voltage limit measurement 01B MMODEUV undervoltage limit measurement 10B MMODEOV overvoltage limit measurement 11B RESERVED reserved MMODE_...

Page 853: ...er level 00H min threshold value 0 FFH max threshold value 255 CH2_UP 23 16 rw Channel 2 upper trigger level 00H min threshold value 0 FFH max threshold value 255 CH1_UP 15 8 rw Channel 1 upper trigge...

Page 854: ...er level 00H min threshold value 0 FFH max threshold value 255 CH6_UP 23 16 rw Channel 6upper trigger level 00H min threshold value 0 FFH max threshold value 255 CH5_UP 15 8 rw Channel 5 upper trigger...

Page 855: ...er level 00H min threshold value 0 FFH max threshold value 255 CH10_UP 23 16 rw Channel 10 upper trigger level 00H min threshold value 0 FFH max threshold value 255 CH9_UP 15 8 rw Channel 9 upper trig...

Page 856: ...vel 00H min threshold value 0 FFH max threshold value 255 DCH3_UP 23 16 rw Differential Channel 3 upper trigger level 00H min threshold value 0 FFH max threshold value 255 DCH2_UP 15 8 rw Differential...

Page 857: ...is 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_CH3 26 24 rw Upper timer trigger threshold channel 3 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 858: ...CH1 10 8 rw Upper timer trigger threshold channel 1 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements R...

Page 859: ...is 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_CH7 26 24 rw Upper timer trigger threshold channel 7 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 860: ...CH5 10 8 rw Upper timer trigger threshold channel 5 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements R...

Page 861: ...4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_CH11 26 24 rw Upper timer trigger threshold channel 11 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 862: ..._CH9 10 8 rw Upper timer trigger threshold channel 9 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements 5H 32 measurements 6H 63 measurements 7H 63 measurements...

Page 863: ...sis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_UP_DCH4 26 24 rw Upper timer trigger threshold differential channel 4 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H...

Page 864: ...8 rw Upper timer trigger threshold differential channel 2 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 15 measurements 5H 15 measurements 6H 15 measurements 7H 15 measurem...

Page 865: ...wer trigger level 00H Min threshold value FFH Max threshold value CH2_LOW 23 16 rw Channel 2 lower trigger level 00H Min threshold value FFH Max threshold value CH1_LOW 15 8 rw Channel 1 lower trigger...

Page 866: ...wer trigger level 00H Min threshold value FFH Max threshold value CH6_LOW 23 16 rw Channel 6 lower trigger level 00H Min threshold value FFH Max threshold value CH5_LOW 15 8 rw Channel 5 lower trigger...

Page 867: ...wer trigger level 00H Min threshold value FFH Max threshold value CH10_LOW 23 16 rw Channel 10 lower trigger level 00H Min threshold value FFH Max threshold value CH9_LOW 15 8 rw Channel 9 lower trigg...

Page 868: ...trigger level 00H Min threshold value FFH Max threshold value DCH3_LOW 23 16 rw Differential Channel 3 lower trigger level 00H Min threshold value FFH Max threshold value DCH2_LOW 15 8 rw Differentia...

Page 869: ...is 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH3 26 24 rw Lower timer trigger threshold channel 3 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 870: ...ST4 hysteresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH1 10 8 rw Lower timer trigger threshold channel 1 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 m...

Page 871: ...crocontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 473 RESET of ADC1_CNT0_3_LOWER Register Reset Type Reset Values Reset Short Name Reset...

Page 872: ...is 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH7 26 24 rw Lower timer trigger threshold channel 7 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 873: ...ST4 hysteresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH5 10 8 rw Lower timer trigger threshold channel 5 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 m...

Page 874: ...crocontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 474 RESET of ADC1_CNT4_7_LOWER Register Reset Type Reset Values Reset Short Name Reset...

Page 875: ...4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH11 26 24 rw Lower timer trigger threshold channel 11 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16 measurements...

Page 876: ...YST4 hysteresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_CH9 10 8 rw Lower timer trigger threshold channel 9 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H 16...

Page 877: ...crocontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 475 RESET of ADC1_CNT8_11_LOWER Register Reset Type Reset Values Reset Short Name Reset...

Page 878: ...sis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_DCH4 26 24 rw Lower timer trigger threshold differential channel 4 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements 4H...

Page 879: ...teresis 4 2H HYST8 hysteresis 8 3H HYST16 hysteresis 16 CNT_LO_DCH2 10 8 rw Lower timer trigger threshold differential channel 2 0H 1 measurement 1H 2 measurements 2H 4 measurements 3H 8 measurements...

Page 880: ...rocontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 476 RESET of ADC1_DCHCNT1_4_LOWER Register Reset Type Reset Values Reset Short Name Rese...

Page 881: ...on Figure 202 shows the interrupt generation of ADC1 The generated interrupts are assigned to several nodes The exact mapping can be red in the corresponding interrupt chapter of this device Note alls...

Page 882: ...S_1 MON1_IS ADC1_IRQEN_1 MON1_IEN ADC1_IRQCLR_1 MON2_ISC ADC1_IRQS_1 MON2_IS ADC1_IRQEN_1 MON2_IEN ADC1_IRQCLR_1 MON3_ISC ADC1_IRQS_1 MON3_IS ADC1_IRQEN_1 MON3_IEN ADC1_IRQCLR_1 MON4_ISC ADC1_IRQS_1 M...

Page 883: ...rupt Control ADC1 Interrupt Control ADC1_IRQCLR_2 MON1_UP_ISC ADC1_IRQS_2 MON1_UP_IS ADC1_IRQEN_2 MON1_UP_IEN ADC1_IRQCLR_2 MON1_LO_ISC ADC1_IRQS_2 MON1_LO_IS ADC1_IRQEN_2 MON1_LO_IEN ADC1_IRQCLR_2 MO...

Page 884: ...P_IS ADC1_IRQEN_2 P2_1_UP_IEN ADC1_IRQCLR_2 P2_1_LO_ISC ADC1_IRQS_2 P2_1_LO_IS ADC1_IRQEN_2 P2_1_LO_IEN ADC1_IRQCLR_2 P2_2_UP_ISC ADC1_IRQS_2 P2_2_UP_IS ADC1_IRQEN_2 P2_1_UP_IEN ADC1_IRQCLR_2 P2_2_LO_...

Page 885: ...ol ADC1 Interrupt Control ADC1_IRQCLR_2 DU1_UP_ISC ADC1_IRQS_2 DU1_UP_IS ADC1_IRQEN_2 DU1_UP_IEN ADC1_IRQCLR_2 DU1_LO_ISC ADC1_IRQS_2 DU1_LO_IS ADC1_IRQEN_2 DU1_LO_IEN ADC1_IRQCLR_2 DU2_UP_ISC ADC1_IR...

Page 886: ..._IRQS_1 ADC1 Interrupt Status 1 Register 64H 0000 0000H ADC1_IRQS_2 ADC1 Interrupt Status 2 Register 100H 0000 0000H ADC1_STS_1 ADC1 Status 1 Register 124H 0000 0000H ADC1_STS_2 ADC1 Status 2 Register...

Page 887: ...hed 0B INACTIVE No DU upper Channel Interrupt has occurred 1B ACTIVE DU upper ChannelInterrupthas occurred DU3LO_IS 28 rwhxre ADC1 Differential Unit 3 DU3 lower Channel Interrupt Status Conversion of...

Page 888: ...ed Always read as 0 ESM_IS 17 rwhxre Exceptional Sequence Measurement ESM Status 0B INACTIVE No ESM has occurred 1B ACTIVE ESM occurred EIM_IS 16 rwhxre Exceptional Interrupt Measurement EIM Status 0B...

Page 889: ...ccurred MON3_IS 4 rwhxre ADC1 Channel 4 Interrupt Status Conversion of Channel has finished 0B INACTIVE No Channel 4 Interrupt has occurred 1B ACTIVE Channel 4 Interrupt has occurred MON2_IS 3 rwhxre...

Page 890: ...NACTIVE no interrupt has occurred 1B ACTIVE interrupt has occurred P2_1_UP_IS 23 rwhxre ADC1 Port 2 1 Upper Threshold Interrupt Status 0B INACTIVE no interrupt has occurred 1B ACTIVE interrupt has occ...

Page 891: ...rupt has occurred 1B ACTIVE interrupt has occurred P2_2_LO_IS 8 rwhxre ADC1 Port 2 2 Lower Threshold Interrupt Status 0B INACTIVE no interrupt has occurred 1B ACTIVE interrupt has occurred P2_1_LO_IS...

Page 892: ...ower Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 RES 0 r Reserved Always read as 0 Table 479 RESET of ADC1_IRQS_2 Register Reset Type Reset Values Reset Short Name Reset...

Page 893: ...Channel Status Conversion of Channel has finished 0B INACTIVE No DU upper Channel Status has occurred 1B ACTIVE DU upper Channel Status has occurred DU3LO_STS 28 rwhxr ADC1 Differential Unit 3 DU3 lo...

Page 894: ...er Channel Status has occurred 1B ACTIVE DU upper Channel Status has occurred DU1LO_STS 24 rwhxr ADC1 Differential Unit 1 DU1 lower Channel Status Conversion of Channel has finished 0B INACTIVE No DU...

Page 895: ...pper Threshold Status 0B Below limit Status below upper threshold 1B Above limit Upper threshold exceeded P2_1_UP_STS 23 rc ADC1 Port 2 1 Upper Threshold Status 0B Below limit Status below upper thres...

Page 896: ...threshold 1B Above limit Upper threshold exceeded P2_2_LO_STS 8 rc ADC1 Port 2 2 Lower Threshold Status 0B Below limit Status below upper threshold 1B Above limit Upper threshold exceeded P2_1_LO_STS...

Page 897: ...Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 RES 0 r Reserved Always read as 0 Table 481 RESET of ADC1_STS_2 Register Reset Type Reset Values Reset Short Name Reset...

Page 898: ...Status has occurred 1B ACTIVE DU lower Channel Status has occurred DU3UP_SC 29 w ADC1 Differential Unit 3 DU3 upper Channel Status Clear Conversion of Channel has finished 0B INACTIVE No DU upper Cha...

Page 899: ...ential Unit 1 DU1 upper Channel Status Clear Conversion of Channel has finished 0B INACTIVE No DU upper Channel Status has occurred 1B ACTIVE DU upper Channel Status has occurred DU1LO_SC 24 w ADC1 Di...

Page 900: ...fferential Unit 2 lower Interrupt Status Clear 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared DU2LO_ISC 26 w Differential Unit 2 lower Interrupt Status Clear 0B INAC...

Page 901: ...red 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared P2_2_ISC 8 w ADC1 Port 2 2 Interrupt Status Clear Interrupt status is cleared 0B INACTIVE interrupt status is not...

Page 902: ...tus is cleared VS_ISC 1 w ADC1 VS Interrupt Status Clear Interrupt status is cleared 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared VBATSEN_ISC 0 w ADC1 VBAT_SENSE I...

Page 903: ...P_ISC 24 w ADC1 Port 2 2 Upper Threshold Interrupt Status Clear Interrupt status is cleared 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared P2_1_UP_ISC 23 w ADC1 Port...

Page 904: ...7_LO_ISC 11 w ADC1 Port 2 7 Lower Threshold Interrupt Status Clear Interrupt status is cleared 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared P2_6_LO_ISC 10 w ADC1 P...

Page 905: ..._ISC 3 w ADC1 MON 2 Lower Threshold Interrupt Status Clear Interrupt status is cleared 0B INACTIVE interrupt status is not cleared 1B ACTIVE interrupt status is cleared MON1_LO_ISC 2 w ADC1 MON 1 Lowe...

Page 906: ...upt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled DU2LO_IEN 26 rw Differential Unit 2 lower Interrupt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled DU1UP_IEN...

Page 907: ...IEN 8 rw ADC1 Port 2 2 Interrupt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled P2_1_IEN 7 rw ADC1 Port 2 1 Interrupt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt ena...

Page 908: ...Microcontroller with LIN and Power Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 Table 485 RESET of ADC1_IRQEN_1 Register Reset Type Reset Values Reset Short Name Reset Mo...

Page 909: ...rw ADC1 Port 2 2 Upper Threshold Interrupt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled P2_1_UP_IEN 23 rw ADC1 Port 2 1 Upper Threshold Interrupt Enable 0B DISABLED Interrupt dis...

Page 910: ...able 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled P2_2_LO_IEN 8 rw ADC1 Port 2 2 Lower Threshold Interrupt Enable 0B DISABLED Interrupt disabled 1B ENABLED Interrupt enabled P2_1_LO_IEN...

Page 911: ...ower Switches for Automotive Applications 10 Bit Analog Digital Converter ADC1 RES 0 r Reserved Always read as 0 Table 486 RESET of ADC1_IRQEN_2 Register Reset Type Reset Values Reset Short Name Reset...

Page 912: ...nt Unit Figure 207 Motivation for Differential Measurement Unit 24 10 2 Implementation of Differential Measurement Unit The differential measurement unit is a sub unit of the digital postprocessing It...

Page 913: ...ive state without CPU Load or Interrupt Handling of Differential Unit TLE9845QX only Due to the fact that this measurements need to be aligned to a certain PWM control scenario there is necessary to b...

Page 914: ...d by the DU unit The DU_int_en x signals are configured in register SCU_MODPISEL4 All DU_int_en x signals are AND gated with COUT63 dpp1_adc_diff dpp_adc_trig DU_ext_en 0 DU_ext_en 1 DU_ext_en 2 DU_ex...

Page 915: ...omotive Applications 10 Bit Analog Digital Converter ADC1 Figure 210 Timing of enable signals for the DU Unit SEQ0 SEQ1 SEQ2 SEQ3 SEQ4 SEQ5 SEQ6 SEQ7 Sequence Seq_change CC60 COUT60 CC61 COUT61 DU_int...

Page 916: ...gister The registers are addressed wordwise Table 487 Register Overview Register Short Name Register Long Name Offset Address Reset Value ADC1 Differential Unit Input Selection Register ADC1_DUIN_SEL...

Page 917: ...27 25 r Reserved Always read as 0 DU4_EN 24 rw Differential Unit 4 enable 0B DU4 disable Differential Unit 4 is disabled 1B DU4 enable Differential Unit 4 is enabled RES 23 21 r Reserved Always read a...

Page 918: ...ifferential Unit 2 is disabled 1B DU2 enable Differential Unit 2 is enabled RES 7 5 r Reserved Always read as 0 DU1RES_NEG 4 rc Differential Unit 1 result negative Note if the calculated result is neg...

Page 919: ...s signals are forced to zero during the start up phase The end of the start up phase is indicated by the ready signal MI_RDY in bit ADC1_CTRL3 MCM_RDY Measurement Core start up procedure the startup t...

Page 920: ...Threshol d analog Hyster esis4 4 Bitfield HYST_UP_CHn HYST_LO_CHn 0 hyst off 1 hyst 4 2 hyst 8 3 hyst 16 Coun ters5 5 Bitfield CNT_UP_CHn CNT_LO_CHn 0 1 meas 1 2 meas 2 4 meas 3 8 meas Ch 0 VBAT_SEN S...

Page 921: ...tions MON inputs can also be evaluated with ADC in Active Mode using adjustable threshold values see also Chapter 24 Selectable pull up and pull down current sources available 25 2 Introduction This m...

Page 922: ...ith open inputs and a filter function to avoid wake up events caused by unwanted voltage transients at the module input When automatic current source selection is enabled a voltage level at the MONx i...

Page 923: ...0 leakage current1 1 all current sources switched off pull up down current source disabled 0 1 pull down pull down current source enabled for low active switches 1 0 pull up pull up current source ena...

Page 924: ...able 493 Register Overview Register Short Name Register Long Name Offset Address Reset Value Register Definition Monitor Input Registers PMU_MON_CNF1 Settings Monitor 1 4 034H 4747 4747H PMU_MON_CNF2...

Page 925: ...le Note Works only if MON4_EN is enabled 0B Pull up source disabled 1B Pull up source enabled MON4_PD 28 rw Pull Down Current Source for MON4 Input Enable Note Works only if MON4_EN is enabled 0B Pull...

Page 926: ...N is enabled 0B Pull up source disabled 1B Pull up source enabled MON3_PD 20 rw Pull Down Current Source for MON3 Input Enable Note Works only if MON3_EN is enabled 0B Pull down source disabled 1B Pul...

Page 927: ...EN is enabled 0B Pull up source disabled 1B Pull up source enabled MON2_PD 12 rw Pull Down Current Source for MON2 Input Enable Note Works only if MON2_EN is enabled 0B Pull down source disabled 1B Pu...

Page 928: ...EN is enabled 0B Pull up source disabled 1B Pull up source enabled MON1_PD 4 rw Pull Down Current Source for MON1 Input Enable Note Works only if MON1_EN is enabled 0B Pull down source disabled 1B Pul...

Page 929: ...STS is not updated when MONx_EN is switched off MONx_STS is also not updated when both wake options MONx_RISE and MONx_FALL are off 0B MON input has low status 1B MON input has high status RES 6 r Res...

Page 930: ...N5_RISE 2 rw MON5 Wake up on Rising Edge Enable Note Works only if MON1_EN is enabled 0B Wake up disabled 1B Wake up enabled MON5_FALL 1 rw MON5 Wake up on Falling Edge Enable Note Works only if MON5_...

Page 931: ...resistive load connections only small line inductances are allowed Overcurrent limitation Overcurrent detection with thresholds 25 mA 50 mA 100 mA 150 mA and automatic shutdown Overtemperature detecti...

Page 932: ...are available The PWM Mode can also be enabled by a HSx_CTRL SFR bit The PWM configuration has to be done in the corresponding PWM Module All protection functions are also available in this mode The m...

Page 933: ...he pwm mode 26 3 1 2 Overcurrent Detection To configure the proper overcurrent threshold the corresponding bits HSx_OC_SEL in the HSx_CTRL SFR have to be set If an overcurrent condition is present the...

Page 934: ...ched on down to Vs 3V 26 3 2 PWM Operation In PWM mode the high side switch has to be first enabled by the corresponding bits in the HSx_CTRL register The related bits are described below PWM_CHx in F...

Page 935: ...S_CTRL High Side Driver Control 04H 0000 0000H HS_IRQS High Side Driver Interrupt Status 08H 0000 0000H HS_IRQCLR High Side Driver Interrupt Status Clear Register 0CH 0000 0000H HS_IRQEN High Side Dri...

Page 936: ...erved Always read as 0 HS2_OL_EN 19 rw High Side 2 Open Load Detection Enable 0B DISABLE disable open load detection 1B ENABLE enable open load detection HS2_ON 18 rwhrs High Side 2 On 0B OFF HS drive...

Page 937: ...her priority then HS1_ON 0B DISABLE disables control by PWM input 1B ENABLE enables control by PWM input HS1_EN 0 rwhrs High Side 1 Enable 0B DISABLE HS circuit power off 1B ENABLE HS circuit power on...

Page 938: ...oad detected write sets status HS2_OT_IS 21 rwhxre High Side 2 Overtemperature Interrupt Status 0B no Overtemperature no overtemperature occurred 1B Overtemperature overtemperature occurred switch is...

Page 939: ...ESET_TYPE_3 00000000H RESET_TYPE_3 HS_IRQCLR Offset Reset Value High Side Driver Interrupt Status Clear Register 0CH see Table 500 Field Bits Type Description RES 31 r Reserved Always read as 0 HS2_OL...

Page 940: ...HS1_OT_SC 13 w High Side 1 Overtemperature Status Clear 0B no Clear 1B Clear RES 12 8 r Reserved Always read as 0 HS1_OC_ISC 7 w High Side 1 Overcurrent Interrupt Status Clear 0B no Clear 1B Clear HS1...

Page 941: ...e RES 20 8 r Reserved Always read as 0 HS1_OC_IEN 7 rw High Side 1 Overcurrent interrupt enable 0B disable 1B enable HS1_OL_IEN 6 rw High Side 1 Open Load interrupt enable 0B disable 1B enable HS1_OT_...

Page 942: ...PWM output of CCU6 0101BCOUT62 PWM output of CCU6 0110BT3OUT PWM output of GPT12 HS2_SRC_SEL 2 0 rw HS2 PWM Source Selection Note Can only be written when HS_CTRL HS2_PWM 0 0000BCC60 PWM output of CCU...

Page 943: ...rrent Overtemperature Detection 00B 4_us 4 s filter time 01B 8_us 8 s filter time 10B 16_us 16 s filter time 11B 32_us 32 s filter time RES 7 4 r Reserved Always read as 0 RES 3 2 r Reserved Always re...

Page 944: ...read as 0 RES 13 10 r Reserved Always read as 0 HS2_OC_OT_BTFILT_SEL 9 8 rw Blanking Time Filter Select for HS2 Overcurrent Overtemperature Detection 00B 4_us 4 s filter time 01B 8_us 8 s filter time...

Page 945: ...ame interrupt status register Open load detection the open load detection interrupt flag is a level sensitive interrupt flag This flag is set when the open condition occurs but can be cleared immediat...

Page 946: ...ations High Side Switch Figure 217 Circuitry Mandatory for use as Offboard Pin If the High Side module is used as offboard pin a 6 8 nF is needed as buffer capacitor High Side Driver OC Detection OL D...

Page 947: ...onal Features Multi purpose low side switch optimized for driving relays simple relay driver PWM relay driver Integrated clamping for usage as a simple relay driver overcurrent detection and automatic...

Page 948: ...xceed 25 kHz fast slew rate only 27 2 1 Normal Operation In normal operation mode CPU normal mode CPU slow down mode the low side switch provides functionalities and protection functions which are sel...

Page 949: ...s still present the switch will be disabled once again 27 2 1 3 Overtemperature Detection If overtemperature condition appears the switch will shutdown and the corresponding bit LSx_OT_STSis set To re...

Page 950: ...User Manual 950 Rev 1 1 2019 03 18 TLE984xQX Microcontroller with LIN and Power Switches for Automotive Applications Low Side Switch...

Page 951: ...not designed to handle the amount of energy which is generated by switching an inductive load in PWM Mode Therefore an external free wheeling diode is required to absorb the generated energy The pictu...

Page 952: ...see Table 507 LS_IRQS Low Side Driver Interrupt Status 08H see Table 508 LS_IRQCLR Low Side Driver Interrupt Status Register Clear 0CH see Table 509 LS_IRQEN Low Side Driver Interrupt Enable Register...

Page 953: ...priority then LS2_ON 0B DISABLE normal mode controlled by LS2_ON 1B ENABLE enables LS2 for PWM mode LS2_EN 16 rw Low Side switch 2 Enable 0B DISABLE disables LS2 1B ENABLE enables LS2 RES 15 9 r Rese...

Page 954: ...rature occurred 1B Overtemperature overtemperature occurred switch is automatically shutdown Write sets status LS2_OT_PREWARN_STS 28 rwhxr Low Side 2 Overtemperature Prewarning Status 0B no Overtemper...

Page 955: ...w Side 1 Open Load Status 0B no Open Load no open load Condition occurred 1B Open Load open load occurred switch is not automatically shutdown Write sets status LS1_OT_STS 13 rwhxr Low Side 1 Overtemp...

Page 956: ...occurred switch is automatically shutdown Write sets status LS1_OT_PREWARN_IS 4 rwhxre Low Side 1 Overtemperature Prewarning Interrupt Status 0B no Overtemperature Prewarn no overtemperature prewarn...

Page 957: ...clear 0H No Clear 1H Clear RES 27 24 r Reserved Always read as 0 LS2_OC_ISC 23 w Low Side 2 Overcurrent interrupt status clear 0H No Clear 1H Clear LS2_OL_ISC 22 w Low Side 2 Open Load interrupt stat...

Page 958: ...1 8 r Reserved Always read as 0 LS1_OC_ISC 7 w Low Side 1 Overcurrent interrupt status clear 0H No Clear 1H Clear LS1_OL_ISC 6 w Low Side 1 Open Load interrupt status clear 0B no Clear 1B Clear LS1_OT...

Page 959: ...e 2 Overtemperature interrupt enable 0B disabled 1B enable LS2_OT_PREWARN_IEN 20 rw Low Side 2 Overtemperature prewarn interrupt enable 0B disabled 1B enable RES 19 8 r Reserved Always read as 0 LS1_O...

Page 960: ...1_SRC_SEL 5 3 rw LS1 PWM Source Selection Note Can be only written when LS_CTRL LS1_PWM 0 0000BCC60 PWM output of CCU6 0001BCC61 PWM output of CCU6 0010BCC62 PWM output of CCU6 0011BCOUT60 PWM output...

Page 961: ...RESET_TYPE_3 LS_LS1_TRIM Offset Reset Value Low Side Trimming Register 18H see Table 512 Field Bits Type Description RES 31 10 r Reserved Always read as 0 LS1_OC_BTFILT_SEL 9 8 rw Overcurrent BlankTim...

Page 962: ...ct for LS2 00B 4_us 4 s filter time 01B 8_us 8 s filter time 10B 16_us 16 s filter time 11B 32_us 32 s filter time RES 7 2 r Reserved Always read as 0 LS2_OL_BTFILT_SEL 1 0 rw Open load Blank Time Sel...

Page 963: ...in the dedicated status register which is placed in the same interrupt status register Open Load detection the open load detection interrupt flag is a level sensitive interrupt flag This flag is set...

Page 964: ...ication diagram Figure 222 Simplified Application Diagram Example Note This is a very simplified example of an application circuit and bill of material The function must be verified in the actual appl...

Page 965: ...n 3 ceramic capacitor CVDDEXT Capacitor at VDDEXT pin 330 nF2 CVDDC Capacitor at VDDC pin 100 nF2 3 330 nF2 CVDDP Capacitor at VDDP pin 470 nF2 3 470 nF2 RMONx Resistor at MONx pin 3 9 k CMONx Capacit...

Page 966: ...ion setup controlling an uni directional brushed DC motor The driver stages support two variants to drive the motor The non controlled motor contact can be connected to battery or to ground potential...

Page 967: ...of the half bridge In this case HSx and LSx are switched without any deadtime The gate pre resistors has to be dimensioned expecting the max values 28 2 2 3 MOSFET protection with integrated Differen...

Page 968: ...ng the debug mode unintendedly in the final application adding an external pull down additionally is recommended 28 7 ESD Immunity According to IEC61000 4 2 Note Tests for ESD robustness according to...

Page 969: ...ested by external test house IBEE Zwickau EMC Test report Nr 11 01 16 according to LIN Conformance Test Specification Package for LIN 2 1 October 10th 2008 and Hardware Requirements for LIN CAN and Fl...

Page 970: ...needs ADC1 running Chapter 24 ADC1_CTRL_STS SOOC removed ADC1_STATUS removed contained SD_FEEDB_ON SOC_JITTER DAC_IN added information for ESM_STS this bit has to be cleared additionally to ESM_IS be...

Page 971: ...dapted to 0 was already correct in SCU DM Chapter 13 Chapter 26 Chapter 27 no OC_STS bit signal only for HS and LS overcurrent Chapter 22 Tables ADC2 Channel Selection and Voltage Ranges and ADC1 Chan...

Page 972: ...and any applicable legal requirements norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications The data contained in this docum...

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