Infineon SPI F-RAM FM33256B, Manual

Page: 17 / 19

Application Note 17 of 19 001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F- RAM™ Processor Companion - FM33256B
Pseudo Code Examples
r e s t r i c t e d
10.7 SPI Processor Companion Read
/************PSoC3 Based Pseudo Code for SPI Processor Companion Read*******/
uint8 READ_RTC ( uint8 addr, uint8 *data_read_ptr, uint8 total_data_count)
{
uint8 i;
// Clear the Transmit Buffer
nvRAM_SPI_1_SPIM_ClearTxBuffer();
// Make chip select LOW CS = 0
nvRAM_SPI_1_CS_Reg_Write(0);
// Send Processor Companion Read Command
nvRAM_SPI_1_SPIM_WriteTxData(nvRAM_RTC_READ_CMD);
// Send Processor Companion Read Register Address
nvRAM_SPI_1_SPIM_WriteTxData((uint8)(addr));
// Wait for the transfer to complete
while((nvRAM_SPI_1_SPIM_ReadTxStatus() & nvRAM_SPI_1_SPIM_STS_SPI_DONE) !=
nvRAM_SPI_1_SPIM_STS_SPI_DONE);
// Read the data and store in data_read_ptr
for(i = 0; i < total_data_count; i++ )
{
// Clear receive buffer
nvRAM_SPI_1_SPIM_ClearRxBuffer();
// Send a dummy byte
nvRAM_SPI_1_SPIM_WriteTxData((uint8)0x00);
// Wait for the transfer to complete
while((nvRAM_SPI_1_SPIM_ReadTxStatus() & nvRAM_SPI_1_SPIM_STS_SPI_DONE)
!=
nvRAM_SPI_1_SPIM_STS_SPI_DONE);
// Wait till the receive buffer has received a byte
while(!nvRAM_SPI_1_SPIM_GetRxBufferSize());
// Copy the read byte to data_read_ptr
data_read_ptr[i] = nvRAM_SPI_1_SPIM_ReadRxData();
}
// Make chip select HIGH CS = 1
nvRAM_SPI_1_CS_Reg_Write(1);
}