Infineon S6BT112A Getting Started Download

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Application Note

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002-27376 Rev. *A

2021-06-15

Getting Started with CXPI Transceiver S6BT112A

Revision history

Document
version

Date of release

Description of changes

2019-10-11

New application note.

2021-06-15

Updated to Infineon template.

Summary of Contents for S6BT112A

Page 1: ...ion with the CXPI data link controller MCU and the CXPI bus line In addition it explains how the data link controller shifts the operation mode and arbitrates transmission with the CXPI protocol Associated Part Family S6BT112A Related Documents S6BT112A Datasheet Table of contents About this document 1 Table of contents 1 1 CXPI communication protocol 3 2 S6BT112A CXPI transceiver 4 3 Hardware con...

Page 2: ...etting Started with CXPI Transceiver S6BT112A CXPI communication protocol 4 3 Baud rate detection period and fail safe decode initialization 15 4 3 1 Baud rate detection period 15 4 3 2 Fail safe decode initialization 16 5 Glossary 17 Revision history 18 ...

Page 3: ...ween each node The slave node does not need an external oscillator to extract the data from the bus It will use the master clock because the master node sends a clock pulse with data and the slave node synchronizes with the master clock bit by bit Most general purpose microcontrollers supports CXPI because it uses UART PHY CXPI has the following main features Application layer Supports sleep and w...

Page 4: ...T112A to both the master node and the slave node significant noise reduction can be obtained Table 1 S6BT112A EMI reduction countermeasure circuit Feature Measures and effects Applicable node Optimal slew rate control Harmonics are reduced by lowering the slew rate Master Slave Optimal control of duty cycle of the master clock By optimally controlling the master clock duty cycle harmonics in the k...

Page 5: ...NSLP I Sleep control pin 0 Sleep mode 1 Normal mode standby mode 3 CLK I For master node SELMS 0 Baud rate clock input pin O Slave node SELMS 1 Baud rate clock output pin NSLP HIGH Decoding BUS clock output NSLP LOW Bus clock output without decoding 4 TXD I Transmit UART data input pin 5 GND Ground pin 6 BUS I O Bus line input output pin 7 BAT Battery power input pin 8 SELMS I Master slave switchi...

Page 6: ...er node circuit connection example using Traveo II MCU 220 pF 5 V or 3 3 V S6BT112A RXD NSLP CLK TXD SELMS BAT BUS GND 1 2 3 4 8 7 6 5 GND B BUS GND GND GND GND 10 kΩ 10 µF 10 kΩ 0 1 µF GND CYT2B9 VDDD GND P20 5 CXPI3_RX P12 5 GPIO P14 6 PWM P20 6 CXPI3_TX R4 R3 D1 GND R6 1N4148 D3 1 kΩ TVII R2 10 kΩ Figure 2 Example of master node connection consisting of Traveo II MCU and S6BT112A 3 2 Slave node...

Page 7: ...n_n P3 0 io P1 1 uart_tx R4 R2 10 kΩ D1 Figure 3 Connection example of slave node configured with PSoC 4 and S6BT112A In case of adding the secondary clock master operation the SELMS pin must be connected to the GPIO of the MCU in addition to being pulled up When switching to the secondary clock master operation in the power on state make sure that the NSLP pin is set to LOW and transition to the ...

Page 8: ...T112A Software configuration 4 Software configuration 4 1 Mode transition 4 1 1 Mode transition diagram Figure 4 shows the mode transition diagram of S6BT112A Figure 4 Mode transition diagram of S6BT112A S6BT112A mainly has the following three operating modes Sleep mode Standby mode Normal mode ...

Page 9: ... the TXD terminal is encoded and output to the BUS line The received BUS data is decoded and output to the RXD terminal In addition to the operating modes there are ThermalShutdown mode and WP_ThermalShutdown mode as failsafe functions to prevent malfunctions at abnormally high device temperature In Thermal Shutdown mode the clock or data from the MCU to the BUS will be stopped but the decoded BUS...

Page 10: ...n of S6BT112A to HIGH to transition back to Normal mode In addition the master node will transmit the baud rate clock to the transceiver CLK pin to transmit the clock to the communication bus In the slave node when S6BT112A receives the BUS clock it outputs the non decoded clock signal from the CLK terminal With that as a trigger the MCU sets the NSLP pin of S6BT112A to HIGH within Twakeup_s time ...

Page 11: ...iming from Sleep mode to Normal mode Master node trigger 4 1 3 2 Slave node trigger After detecting an internal wakeup event the slave node sends a Wakeup pulse to the communication bus via the TXD pin In the master node when S6BT112A receives the BUS wakeup pulse it transmits the non decoded wakeup pulse to the RXD terminal In response to this the MCU sets NSLP pin to HIGH within Tclock_start_m t...

Page 12: ...ill set the NSLP pin to LOW to return to Sleep mode Then the Wakeup pulse can be retransmitted A slave node can transmit a Wakeup pulse for maximum of two times including retransmission of the Wakeup pulse If the clock is not transmitted from the master node even after retransmission the wakeup sequence can be performed again after Sleep in physical bus error processing See JASO D015 3 for Tclock_...

Page 13: ...side and bytewise arbitration between UART frames is performed on the MCU side Figure 11 shows the timing chart of S6BT112A bitwise arbitration When PID transmission is in Normal mode S6BT112A compares the transmitted bit with the bit received from the CXPI BUS If they match the BUS output continues If they do not match it means that the node lost the arbitration the BUS output of S6BT112A becomes...

Page 14: ...g As described in the S6BT112A datasheet S6BT112A has transmission reception delay To implement the arbitration function correctly ensure that you implement the following two functions on the MCU side 1 Check whether UART reception is in progress before transmission 2 Verify the transmitted data and received data after the transmission There are two ways to check whether UART reception is in progr...

Page 15: ...3 BUS clocks The timing chart of baud rate detection period at power on is shown in Figure 13 Figure 13 Baud rate detection timing At power ON After transitioning from Normal mode to Sleep mode with the power on the NSLP pin is set to HIGH again to transition to Normal mode Data transmission and reception is available after transition from Standby mode to Normal mode using the clock cycle and the ...

Page 16: ...ly short LOW width is received due to the influence of noise the subsequent clock is erroneously determined as a logical value 0 If 10 logical 0 values are received continuously S6BT112A automatically initializes the decoding process to return to normal operation External initialization processing is not necessary The fail safe decode initialization timing chart is shown in Figure 15 Figure 15 Fai...

Page 17: ...er S6BT112A Glossary 5 Glossary Table 3 Glossary Terms Description CR Collision Resolution CRC Cyclic Redundancy Check CSMA Carrier Sense Multiple Access CXPI Clock Extension Peripheral Interface IBS Inter Byte Space IFS Inter Frame Space PID Protected Identifier PWM Pulse Width Modulation ...

Page 18: ...7376 Rev A 2021 06 15 Getting Started with CXPI Transceiver S6BT112A Revision history Revision history Document version Date of release Description of changes 2019 10 11 New application note A 2021 06 15 Updated to Infineon template ...

Page 19: ...ellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this...

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