User’s Manual
6-43
05.99
On-Chip Peripheral Components
C513AO
6.3.6 Details about Modes 2 and 3
Eleven bits are transmitted through TXD or received through RXD: a start bit (0), eight data bits
(LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can
be assigned a value of “0” or “1”. On receive, the 9th data bit goes into RB8 in SCON. The baudrate
is programmable to either 1/32nd or 1/64th of the oscillator frequency in Mode 2. (When bit SMOD
in SFR PCON (87H) is set in Mode 2, the baudrate is
f
OSC
/32). Mode 3 may have a variable baudrate
generated from either Timer 1 or 2 depending on the state of TCLK and RCLK (SFR T2CON).
Figure 6-25 shows a functional diagram of the serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the
transmit shift register. The timing associated with transmit/receive is illustrated in Figure 6-26.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the
TX control unit that a transmission is requested. Transmission starts at the next rollover in the
divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal).
Transmission begins with activation of SEND, which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift
pulse occurs one bit time after that. The first shift clocks a “1” (the stop bit) into the 9th bit position
of the shift register. Thereafter, only “0”s are clocked in. Thus, as data bits shift out to the right, “0”s
are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit
is just to the left of TB8, and all positions to the left of that contain “0”s. This condition flags the TX
control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-
by-16 rollover after “WRITE to SBUF”.
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose, RXD is sampled at
a rate of sixteen times whatever baudrate has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD.
The value accepted is the value that was seen in at least two of the three samples. If the value
accepted during the first bit time is not “0”, the receive circuits are reset and the unit goes back to
looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
As data bits come from the right, “1”s shift out to the left. When the start bit arrives at the leftmost
position in the shift register (in Modes 2 and 3 this is a 9-bit register), it flags the RX control block to
do one last shift, load SBUF and RB8, and to set RI. The signal to load SBUF and RB8, and to set
RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse
is generated:
1) RI = 0, and
2) Either SM2 = 0 or the received 9th data bit = 1
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If
both conditions are met, the received 9th data bit goes into RB8, and the first eight data bits go into
SBUF. One bit time later, whether the above conditions were met or not, the unit resumes looking
for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to
SBUF, RB8 or RI.
