User’s Manual
3-3
05.99
Memory Organization
C513AO
3.4
XRAM Operation
The XRAM in the C513AO is a memory area that is logically located at the upper end of the external
data memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory, the same instruction types must be used for accessing the XRAM.
The C513AO maps 256 bytes of the external data space into the on-chip XRAM. This could prevent
access to the external memory extension and might induce problems when porting software,
especially when using the 8-bit addressing modes. Therefore, it is possible to enable and disable
the on-chip XRAM using the bit XMAP in SFR SYSCON. When the XRAM is disabled (default after
reset), all external data memory accesses will go to the external data memory area.
3.4.1 Reset Operation of the XRAM
The content of the XRAM is not affected by a reset. After power-up, the content is undefined;
whereas, it remains unchanged during and after a reset if the power supply is not turned off.
However, if a reset occurs during a write operation to XRAM, the effect on the content of an XRAM
memory location depends on the cycle in which the active reset signal is detected (MOVX is a
2-cycle instruction):
Reset during 1st cycle:
The new value will not be written to XRAM. The old value is not affected.
Reset during 2nd cycle: The old value in XRAM is overwritten by the new value.
After reset, access to the XRAM is disabled (bit XMAP of SYSCON = 0).
3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
– The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for
indirect addressing. These instructions are:
– MOVX
A, @DPTR (Read)
– MOVX
@DPTR, A
(Write)
Using these instructions with the XRAM disabled implies that Port 0 is used as the address low/data
bus, Port 2 is used for high address output, and two lines of Port 3 (P3.6/WR/INT2, P3.7/RD) are
used for control to access up to 64 KB of external memory. If the XRAM is enabled and if the
effective address stored in DPTR is in the range of 0000
H
to FEFF
H
, these instructions will access
external memory.
If XRAM is enabled and if the address is within the range FF00
H
to FFFF
H
, the physically internal
XRAM of the C513AO will be accessed. External memory, which is located in this address range,
cannot be accessed in this case because no external bus cycles will be generated. Therefore, Ports
0, 2, and 3 can be used as general purpose I/O if only the XRAM memory space is addressed by
the user program.
