Memory Organization
C513AO
User’s Manual
3-2
05.99
3.1
Program Memory, “Code Space”
The C513AO-2E/2R device has 16 Kbytes of program memory and can be externally expanded up
to 64 Kbytes. If the EA pin is held high, the C513AO-2E/2R executes program code from the on-chip
program memory unless the program counter address exceeds 3FFF
H
. Address locations 4000
H
through FFFF
H
are then fetched from the external program memory. If the EA pin is held low, the
C513AO (all versions) fetches all instructions from the external program memory. For C513AO-2R
with ROM protection, the EA pin is sampled and latched on reset. In this case, the instruction
fetches for PC < 4000
H
are always made from the on-chip program memory. This is also true for
C513AO-2E with programmed protection Level 1 or Level 2. If the on-chip program memory has
been programmed with protection Level 3, the C513AO-2E/2R always starts program execution
from the on-chip program memory unless an external code fetch is initiated by a program counter
value exceeding 3FFF
H
.
3.2
Data Memory, “Data Space”
The data memory address space consists of both an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks: the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128-byte Special Function Register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register-indirect addressing. The upper 128 bytes of RAM can be
accessed through register indirect addressing. The special function registers are accessible
through direct addressing. Four 8-register banks, each consisting of eight 8-bit general-purpose
registers, occupy locations 0 through 1F
H
in the lower RAM area. The next 16 bytes, locations 20
H
through 2F
H
, contain 128 directly-addressable bit locations. The stack can be located anywhere in
the internal RAM area and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions
which use a 16-bit or an 8-bit address. The internal 256 Kbytes of XRAM are located in the external
memory address area at addresses FF00
H
to FFFF
H
.
3.3
General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks of eight General Purpose
Registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the Program
Status Word (PSW) select the active register bank. These bits are RS0 (PSW.3) and RS1 (PSW.4),
(see description of the PSW in Chapter 2). This allows fast context switching, which is useful when
entering subroutines or interrupt service routines.
The eight General Purpose Registers of the selected register bank may be accessed by register
addressing. With register addressing, the instruction op-code indicates which register is to be used.
For indirect addressing, R0 and R1 are used as pointer or index registers to address internal or
external memory (such as: MOV @R0).
Reset initializes the stack pointer to location 07
H
and increments it once to start from location 08
H
(which is also the first register (R0) of Register Bank 1). Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.
