User’s Manual
9-7
05.99
Power Saving Modes
C513AO
9.3.2 Exit from Power-down Mode
The C513AO can recover from Power-down Mode in one of the following ways:
– Hardware reset
– Wake-up from power-down through pin P3.2/INT0
If the bit EWPD in SFR PCON is “0” during power-down entry, the only way to exit from Power-down
Mode is a hardware reset. This reset will restore the SFRs with their default values, but will not
change the contents of the internal RAM and XRAM. The reset signal which terminates Power-
down Mode also restarts the RC oscillator and the on-chip oscillator. The reset operation should not
be activated before
V
DD
is
restored
to
its
normal
operating level and must be held active long
enough to allow the oscillator to restart and stabilize (similar to power-on reset).
There is also the capability to wake-up from power-down. If this capability is used, its function must
be enabled using the following instruction sequence prior to entering Power-down Mode.
ORL
SYSCON,#00010000B
;set RMAP
ORL
PCON1,#80H
;enable external wake-up from power-down by setting EWPD
ANL
SYSCON,#11101111B
;reset RMAP (for future SFR accesses)
Note: Before entering Power-down Mode, the port latch of SFR P3.2 (P3.2/INT0 pin) should contain
a “1
”
(pin operates as input). Otherwise, the wake-up sequence will be started immediately
when Power-down Mode is entered.
Figure 9-1 shows the procedure which must be executed when Power-down Mode is exited via the
INT0 wake-up capability of the C513AO.
If Power-down Mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to
entering Power-down Mode, the Power-down Mode can be exited via P3.2/INT0 while executing
the following procedure:
1. In Power-down Mode, pin P3.2/INT0 must be held at high level.
2. Power-down Mode is terminated when P3.2/INT0 goes low. With P3.2/INT0 = low, the internal
RC oscillator is started. The state of P3.2/INT0 is then latched by the RC oscillator clock signal.
Therefore, P3.2/INT0 should be held low for at least 10
µ
s (latch phase). After this delay, P3.2/
INT0 can be set to high level again if required. Thereafter, the Oscillator Watchdog unit controls
the wake-up procedure in its start up phase.
3. The Oscillator Watchdog unit starts operation as described in Section 8.2.1. When the on-chip
oscillator clock is detected for stable nominal frequency, the microcontroller waits for a delay
(typically 5 ms) and then starts again with its operation initiating the power-down wake-up
interrupt. The interrupt address of the first instruction to be executed after wake-up is 007B
H
.
4. After the RETI instruction of the power-down wake-up interrupt routine has been executed, the
instruction which follows the one which initiated Power-down Mode will be executed. The
peripheral unit’s timer 0/1/2, serial interface, SSC interface, and WDT are frozen until end of
Phase 4.
