User’s Manual
9-5
05.99
Power Saving Modes
C513AO
9.2
Slow-down Mode Operation
In some applications, where power consumption and dissipation are critical, the controller might run
for a certain time at reduced speed (for example, if the controller is waiting for an input signal). As
a CMOS device, the C513AO has an almost linear dependence of the operating frequency and the
power supply current, so that a reduction of the operating frequency results in reduced power
consumption.
In Slow-down Mode, all signal frequencies derived from the oscillator clock are divided by 8.
Slow-down Mode is activated by setting the bit SD in SFR PCON. If Slow-down Mode is enabled,
the clock signals for the CPU and the peripheral units are reduced to 1/8th of the nominal system
clock rate. The controller enters Slow-down Mode after a short synchronization period (max. two
machine cycles). Slow-down Mode is terminated by clearing bit SD.
Slow-down Mode can be combined with Idle Mode by performing the following instruction:
ORL
PCON,#00010001B
; entering idle mode combined with the slow down mode:
; (IDLE and SD set)
There are two ways to terminate the combined Idle and Slow-down Mode:
– Idle Mode can be terminated by activation of any enabled interrupt. When CPU operation is
resumed, the interrupt will be serviced, and the next instruction to be executed after the RETI
instruction will be the one following the instruction that had set the bits IDLE and SD.
Nevertheless, Slow-down Mode remains enabled and if required must be terminated by
clearing the bit SD in the corresponding interrupt service routine or at any point in the program
where the user no longer requires the Slow-down Mode power-saving benefit.
– The other way to terminate the combined Idle and Slow-down Mode is with a hardware reset.
Since the oscillator is still running, the hardware reset must be held active for only two
machine cycles for a complete reset.
