On-Chip Peripheral Components
C513AO
User’s Manual
6-54
05.99
The SCIEN Register enables or disables interrupt request for the status bits. SCIEN must be written
only when the SSC interrupts are disabled in the general Interrupt Enable Register IE (A8H) using
bit ESSC, otherwise, unexpected interrupt requests may occur.
Special Function Register SCIEN (Address F9H)
Reset Value: XXXXXX00B
Note: The SSC interrupt behaviour is also affected by bit ESSC in the Interrupt Enable Register IE
and by bit PSSC in the Interrupt Priority Register IP.
Bit
Function
–
Reserved for future use.
WCEN
SSC Write Collision interrupt Enable
WCEN = 0: No interrupt request will be generated if the WCOL bit in the status
register SCF is set.
WCEN = 1: An interrupt is generated if the WCOL bit in the status register SCF is set.
TCEN
SSC transfer completed interrupt enable
TCEN = 0:
No interrupt request will be generated if the TC bit in the status register
SCF is set.
TCEN = 1:
An interrupt is generated if the TC bit in the status register SCF is set.
–
–
–
–
F9H
SCIEN
Bit No.
7
6
5
4
3
2
1
0
MSB
LSB
–
–
WCEN TCEN
