XC2200 Derivatives
System Units (Vol. 1 of 2)
The External Bus Controller EBC
User’s Manual
9-3
V2.1, 2008-08
EBC_X8, V1.0d1
9.1
External Bus Signals
The External Bus uses the following I/O signals
1)
:
1) In the 64-pin package the External Bus is not available.
Table 9-1
EBC Bus Signals
Signal
I/O Port
Pins
Description
Signals available both in the 100-pin and 144-pin package
ALE
O
P10
Address Latch Enable; active high
RD
O
ReaD strobe: activated for every read access (active low)
WR, WRL
O
WRite/WRite Low byte strobe (active low)
WR-mode: activated for every write access.
WRL-mode: activated for low byte write accesses on a 16-bit
bus and for every data write access on an 8-bit bus.
BHE, WRH
O
P2
Byte High Enable/WRite High byte strobe (active low)
BHE-mode: activated for every data access to the upper
byte of the 16-bit bus (handled as additional address bit)
WRH-mode: activated for high byte write accesses on a
16-bit bus.
READY/
READY
I
P2
READY; used for dynamic wait state insertion;
programmable active high or low
AD[12..0]
AD[15..13]
I/O P10
P2
Address/Data bus; in multiplexed mode this bus is used for
both address and data, in demultiplexed mode it is data bus
only
A[7..0]
A[15..8]
A[23..16]
O
P0
P1
P2
Address bus
CS[3..0]
O
P4
Chip Select; active low;
CS7-used for internal LXBus access to MultiCAN and USICs
Signals available additionally in the 144-pin package
BREQ
O
P3
Bus REQuest; active low
HLDA
I/O
HoLD Accepted output (by the master); active low
HoLD Accepted input (at the slave); active low
HOLD
I
HOLD request; active low
CS4
O
P6
Chip Select; active low;
CS7-used for internal LXBus access to MultiCAN and USICs
