TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual
24-110
V2.0, 2007-07
GPTA, V2.0
24.2.4.5 Multiplexer Register Array Programming
A total of 52 control registers are required to program the configuration of the output
multiplexer and the two input multiplexers of the Input/Output Line Sharing Unit. These
IOLS control registers are combined into a Multiplexer Register Array FIFO that can only
be read or written sequentially. Therefore, the control registers values cannot be
accessed directly but must be accessed in a specific sequential order.
Three registers are available for controlling the Multiplexer Register Array:
•
Multiplexer Register Array Control Register MRACTL
•
Multiplexer Register Array Data In Register MRADIN
•
Multiplexer Register Array Data Out Register MRADOUT
shows the structure of the multiplexer array FIFO with the arrangement of
the multiplexer control registers.
For programming of the multiplexer array FIFO, the following steps must be executed:
1. Disable interconnections of the multiplexer array by writing MRACTL.MAEN = 0
(default after reset). The multiplexer array is disabled, all cell input lines are driven
with 0, and device pins assigned to GPTA I/O lines or output lines are disconnected.
2. Reset the write cycle counter to 0 by writing MRACTL.WCRES = 1.
3. Write sequentially the multiplexer control register contents one after the other
(52 values) into MRADIN, starting with the register values for OMCRH13, OMCRL13,
… up to GIMCRH0, GIMCRL0 (see
). After the first MRADIN write
operation, the content for OMCRH13 is at FIFO position 1. With each following
MRADIN write operation, it becomes shifted one FIFO position upwards. After the 52.
MRADIN write operation, the OMCRH13 value is at its final position. The contents of
FIFO position 52 can be read via register MRADOUT. With each MRADIN write
operation the write cycle counter MRACTL.FIFOFILLCNT is incremented by 1. After
all FIFO entries have been written, the FIFO is locked, bit MRACTL.FIFOFULL is set,
and further MRADIN write operations are discarded until bit MRACTL.WCRES is
written again with a 0.
4. Enable the multiplexer array by writing MRACTL.MAEN = 1. This establishes and
enables all programmed interconnections.
To check the FIFO contents, the FIFO can be written a second time. At this check
MRADIN is written before MRADOUT is read. This will return the FIFO contents of the
first write sequence in the order of OMCRH13, OMCRL13, …, GIMCRH0, GIMCRL0.
Before disabling the multiplexer array FIFO, GPTA output pins that are already enabled
as GPTA output should be switched to GPIO function to avoid output spikes. After
enabling the multiplexer array FIFO again, the GPTA output can be switched again back
to GPTA output function.
Shifting the write data through the FIFO requires a few clock cycles. When new data
becomes written before the FIFO is ready to accept them, wait states will be inserted into
the write access.
