TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual
22-27
V2.0, 2007-07
MultiCAN, V2.0
22.3.5.4 CAN Frame Counter
Each CAN node is equipped with a frame counter that counts transmitted/received CAN
frames or obtains information about the time when a frame has been started to transmit
or be received by the CAN node. CAN frame counting/bit time counting is performed by
a 16-bit counter that is controlled by Node x Frame Counter Register NFCRx (see
). Bit field NFCRx.CFSEL determines the operation mode of the frame
counter:
•
Frame Count Mode:
The frame counter is incremented after the successful transmission and/or reception
of a CAN frame. The incremented value is copied into the CFCVAL bit field of the
MOIPRn register of the message object involved in the transfer.
•
Time Stamp Mode:
The frame counter is incremented with the beginning of a new bit time. When the
transmission/reception of a frame starts, the value of the frame counter is captured
and stored to the CFC bit field of the NFCRx register. After the successful transfer of
the frame the captured value is copied to the CFCVAL bit field of the MOIPRn register
of the message object involved in the transfer.
•
Bit Timing Mode:
Used for baud rate detection and analysis of the bit timing (see
22.3.5.5 CAN Node Interrupts
Each CAN node has four hardware triggered interrupt request types that are able to
generate an interrupt request upon:
•
The successful transmission or reception of a frame
•
A CAN protocol error with a last error code
•
An alert condition: Transmit/receive error counters reach the warning limit, bus-off
state changes, a List Length Error occurs, or a List Object Error
•
An overflow of the frame counter
Besides the hardware generated interrupts, software initiated interrupts can be
generated using the Module Interrupt Trigger Register MITR. Writing a 1 to bit n of bit
field MITR.IT generates an interrupt request signal on the corresponding interrupt output
line INT_On. When writing MITR.IT more than one bit can be set resulting in activation
of multiple INT_On interrupt output lines at the same time. See also
for further processing of the CAN node interrupts.
