TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual
20-14
V2.0, 2007-07
SSC, V2.1
20.1.2.7 Receive FIFO Operation
The Receive FIFO (RXFIFO) provides the following functionality:
•
Enable/disable control
•
Programmable filling level for receive interrupt generation
•
Filling level indication
•
FIFO clear (flush) operation
•
FIFO overflow error generation
•
2 to 16 bit RXFIFO data width
The RXFIFO is controlled by the RXFCON control register. When bit RXFCON.RXFEN
is set, the RXFIFO is enabled. The interrupt trigger level defined by RXFCON.RXFITL
determines the filling level of RXFIFO at which a receive interrupt request RIR is
generated. RIR is always generated when the filling level of the RXFIFO is equal to or
greater than the value stored in RXFCON.RXFITL.
Bit field RXFFL in the FIFO Status Register FSTAT indicates the number of bytes that
have been actually written into the FIFO and can be read out of the FIFO by a user
program.
The RXFIFO cannot be accessed directly. All data read operations from the RXFIFO are
executed by reading the RB register. The data width of one RXFIFO stage can be from
2 to 16 bits (as programmed in CON.BM).
shows an example of a RXFIFO operation with a typical data width of 8 bits,
representing a byte. In this example, six bytes are received via the receive input line. The
RXFIFO interrupt trigger level RXFCON.RXFITL is set to 0011
B
. Therefore, the first
receive interrupt request RIR is generated after the reception of Byte 3 (RXFIFO is filled
with three messages).
After the reception of Byte 4, three bytes are read out of the RXFIFO. After this read
operation, the RXFIFO still contains one message. RIR becomes again active after two
more bytes (Bytes 5 and 6) have been received (RXFIFO filled again with 3 bytes).
Finally, the FIFO is cleared after three read operations.
If the RXFIFO is full and additional data are received, the receive interrupt request RIR
will be generated and bit CON.RE is set, if CON.REN is not cleared. In this case, the data
byte last written into the RXFIFO is overwritten. With the overrun condition, the RXFIFO
filling level FSTAT.RXFFL is set to maximum. If a RB read operation is executed with the
RXFIFO enabled but empty, a RIR will be generated. In this case, the RXFIFO filling level
FSTAT.RXFFL is set to 0000
B
.
If the RXFIFO is available but disabled (RXFCON.RXFEN = 0) the receive operation is
functionally equivalent to the receive operation of the SSC module without FIFO.
The RXFIFO can be flushed or cleared by setting bit RXFCON.RXFFLU in register
RXFCON. After this RXFIFO flush operation, the RXFIFO is empty and the RXFIFO
filling level FSTAT.RXFFL is set to 0000
B
.
