Infineon Technologies TC1784, User Manual

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TC1784
LMB External Bus Unit
User´s Manual 12-41 V1.1, 2011-05
EBUT13L-A, V1.16
1. In the cycle marked ‘1’ in Figure 12-10 the processor initiates a read sequence by
writing the “Read Command” value to address “NAND_FLAS 0x40000”.
This generates a write sequence with CLE (A(17)) driven high and ALE (A(16)) driven
low.
2. In the cycle marked ‘2’ the processor loads the most significant byte of the read
address by writing to address “NAND_FLAS 0x20000”. This generates a
write sequence with CLE (A(17)) driven low and ALE (A(16)) driven high.
3. In the cycle marked ‘3’ the processor loads the middle significant byte of the read
address by repeating the access specified in ‘2’ above.
4. In the cycle marked ‘4’ the processor loads the least significant byte of the read
address by repeating the access specified in ‘2’ above. The Nand Flash responds to
this final address byte by driving it’s R/B output low. The processor monitors this pin
(using the EBU_MODCON.sts bit) until the Nand Flash has completed it’s internal
data fetch.
5. In the cycle marked ‘5’ the processor reads the first byte of data by reading address
“NAND_FLAS 0x00000”. The processor can subsequently read any
additionally required (sequential) data bytes by repeating cycle ‘5’.
Note: A similar scheme can be used to generate write access sequences.
12.10.7 Dynamic Command Delay and Wait State Insertion
In general, there are two critical phases during asynchronous device accesses. These
phases are:
•
Command Delay Phase (see Page 12-26 ).
• Command Phase (see Page 12-26 ).
In the EBU, internal length programming for the Command Delay Phase is available via
bit fields EBU_BUSAPx.CMDDELAY.
The equivalent control capability for the Command Phase is available for bit fields
EBU_BUSAP.WAITRDC and EBU_BUSAP.WAITWRC.
12.10.7.1 External Extension of the Command Phase by WAIT
The WAIT input can be used to cause the EBU to extend the Command Phase by
inserting additional cycles prior to deactivation of the RD and RD/WR lines. This signal
can be programmed separately for each region to be ignored or sampled either
synchronously or asynchronously (selected via the EBU_BUSCONx.WAIT bit field).
Additionally, the polarity of WAIT can be programmed for active low (default after reset)
or active high function via bit EBU_BUSCONx.WAITINV. The signal will only take effect
after the programmed number of Command Phase cycles has passed. This means that
the signal can only be used to extend the phase, not to shorten it.
When programmed for synchronous operation, WAIT is sampled on every rising edge of
EBU_CLK during the Command Phase. The sampled value is then used on the next