Infineon Technologies TC1784, User Manual

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-27 V1.1, 2011-05
DMA, V3.03
If the next read to a read from a segment 8 address is not identical (64bit aligned) to the
actual read buffer contents, the contents of the read buffer is invalidated. A 64bit LMB
read is generated by the DMA LMB master interface, the requested 8bit, 16bit or 32 bit
data is forwarded to the DMA Bus switch and the read buffer is updated with the new
64bit data and its related address.
A DMA write to a segment 8 address (8bit, 16bit, 32bit write, 64bit write is not supported)
invalidates the read buffer.
11.2.10 DMA Module Bridge Functionality
The DMA module includes bridge functionality:
•
from the FPI Bus to the DMA Peripheral Interface
• from the DMA Peripheral Interface to the FPI Bus and LMB Bus.
FPI Bus -> LMB Bus
The DMA module does not forward transaction from the FPI Bus to the LMB Bus. The
DMA module does not support / include bridge functionality between FPI Bus and
LMB Bus.
FPI Bus -> DMA Peripheral Interface (MLI, Memory Check, Cerberus, ...)
The DMA module forwards transactions from the FPI bus to the DMA Peripheral
Interface (FPI -> MLI, Memory Check, Cerberus, ...). The identification of the target
module on the DMA Peripheral Interface is done by address decoding.
DMA Peripheral Interface -> On Chip Bus (FPI Bus, LMB Bus)
The DMA module forwards transactions from the active modules that are connected to
the DMA Peripheral Interface (Cerberus, MLI, ...) to the FPI Bus and LMB Bus. The
identification of the target On Chip Bus is done by address decoding.