Infineon Technologies TC1784, User Manual

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-30 V1.1, 2011-05
GPTA
®
v5, V1.14
21.3.2.4 Digital Phase Locked Loop Cell (PLL)
The GPTA
®
v5 provides a digital Phase Locked Loop cell (PLL) with a frequency
multiplier function. An input signal edge is used as a trigger to generate a programmable
number of GPTA
®
v5 module clocks
f
GPTA
on the output signal line. The four signal output
lines of the DCM cells can be used as PLL trigger input. The PLL control circuitry
distributes the desired number of GPTA
®
v5 clocks in regular time intervals over the input
signal period length. The PLL can automatically follow an acceleration or deceleration of
the input signal. Alternatively, an external software routine may handle the input signal’s
period length variation.
The PLL includes a 4-channel input multiplexer, a 16-bit timer, a 16-bit step register, a
24-bit reload register, a 24-bit adder, a 24-bit multiplexer, a 25-bit delta register extended
by one sign bit and a PLL control circuitry (see
Figure 21-18 ).
The following registers are assigned to the Phase Locked Loop cell:
•
PLLCTR = Phase Locked Loop Control Register (see Page 21-176 )
• PLLMTI = Phase Locked Loop Microtick Register (see Page 21-177 )
• PLLCNT = Phase Locked Loop Counter Register (see Page 21-178 )
• PLLSTP = Phase Locked Loop Step Register (see Page 21-177 )
• PLLREV = Phase Locked Loop Reload Register (see Page 21-178 )
• PLLDTR = Phase Locked Loop Delta Register (see Page 21-179 )
• SRSC0 = Service Request State Clear Register 0 (see Page 21-219 )
• SRSS0 = Service Request State Set Register 0 (see Page 21-221 )
Three output signals are available on the PLL cell:
•
PLL signal output line
• Uncompensated PLL signal output line
• Service request line
The desired input signal is selected by programming bit field PLLCTR.MUX. The number
of output pulses to be generated within one input signal period must be stored in the
microtick register PLLMTI and (coded in 2-complement data format) in the step register
PLLSTP. The PLLREV reload register must be programmed with a reload value. This
reload value is calculated by subtracting the number of output pulses to be generated
within one input signal period from the input signal’s period length (measured in number
of
f
GPTA
clocks). An automatic compensation of an input signal acceleration or
deceleration is enabled by setting bit PLLCTR.AEN to 1 (Automatic End Mode). After
disabling the Automatic End Mode, the PLL continuously generates output pulses
without synchronization to an input signal edge.
When the counter for the number of remaining output signal pulses PLLCNT decrements
to zero, the PLL service request flag is set. Additionally, a service request signal PLLSR
will be generated if the control register bit PLLCTR.REN is set.