Infineon Technologies TC1784, User Manual

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TC1784
Controller Area Network Controller (MultiCAN)
User´s Manual 19-17 V1.1, 2011-05
MLI, V2.0
19.3.2 Clock Control
The CAN module timer clock
f
CAN
of the functional blocks of the MultiCAN module is
derived from the module control clock
f
CLC
. The Fractional Divider is used to generate
f
CAN
used for bit timing calculation. The frequency of
f
CAN
is identical for all CAN nodes.
The register file operate with the module control clock
f
CLC
. See also “Module Clock
Generation” on Page 19-111 .
The output clock
f
CAN
of the Fractional Divider is based on the system clock
f
CLC
, but only
every n-th clock pulse is taken. The suspend signal (coming as acknowledge from the
MultiCAN module in response to a OCDS suspend request) freezes or resets the
Fractional Divider.
Figure 19-8 MultiCAN Clock Generation
Table 19-2 indicates the minimum operating frequencies in MHz for
f
CLC
that are
required for a baud rate of 1 Mbit/s for the active CAN nodes. If a lower baud rate is
desired, the values can be scaled linearly (e.g. for a maximum of 500 kbit/s, 50% of the
indicated value are required).
The values imply that the CPU (or DMA) executes maximum accesses to the MultiCAN
module. The values may contain rounding effects.
MCA06265
Fractional
Divider
Module Kernel
f
CAN Clock Control
Register
f
CLC
f
SYS Baud Rate
Prescalers
Register
File