WAFER-ULT3/ULT4 3.5" SBC
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DIMM
Dual Inline Memory Modules are a type of RAM that offer a 64-bit data
bus and have separate electrical contacts on each side of the module.
DIO
The digital inputs and digital outputs are general control signals that
control the on/off circuit of external devices or TTL devices. Data can be
read or written to the selected address to enable the DIO functions.
EHCI
The Enhanced Host Controller Interface (EHCI) specification is a
register-level interface description for USB 2.0 Host Controllers.
EIDE
Enhanced IDE (EIDE) is a newer IDE interface standard that has data
transfer rates between 4.0 MBps and 16.6 MBps.
EIST
Enhanced Intel® SpeedStep Technology (EIST) allows users to modify
the power consumption levels and processor performance through
application software. The application software changes the bus-to-core
frequency ratio and the processor core voltage.
FSB
The Front Side Bus (FSB) is the bi-directional communication channel
between the processor and the Northbridge chipset.
GbE
Gigabit Ethernet (GbE) is an Ethernet version that transfers data at 1.0
Gbps and complies with the IEEE 802.3-2005 standard.
GPIO
General purpose input
HDD
Hard disk drive (HDD) is a type of magnetic, non-volatile computer
storage device that stores digitally encoded data.
ICH
The Input/Output Control Hub (ICH) is an Intel® Southbridge chipset.
IrDA
Infrared Data Association (IrDA) specify infrared data transmission
protocols used to enable electronic devices to wirelessly communicate
with each other.
L1 Cache
The Level 1 Cache (L1 Cache) is a small memory cache built into the
system processor.
L2 Cache
The Level 2 Cache (L2 Cache) is an external processor memory cache.
LCD
Liquid crystal display (LCD) is a flat, low-power display device that
consists of two polarizing plates with a liquid crystal panel in between.
Summary of Contents for WAFER-ULT3
Page 14: ......
Page 15: ...WAFER ULT3 ULT4 3 5 SBC Page 1 Chapter 1 1 Introduction...
Page 19: ...WAFER ULT3 ULT4 3 5 SBC Page 5 Figure 1 3 Connectors Solder Side...
Page 25: ...WAFER ULT3 ULT4 3 5 SBC Page 11 Chapter 2 2 Packing List...
Page 29: ...WAFER ULT3 ULT4 3 5 SBC Page 15 Chapter 3 3 Connectors...
Page 60: ...WAFER ULT3 ULT4 3 5 SBC Page 46 Chapter 4 4 Installation...
Page 84: ...WAFER ULT3 ULT4 3 5 SBC Page 70 Chapter 5 5 BIOS...
Page 119: ...WAFER ULT3 ULT4 3 5 SBC Page 105 Appendix A A Regulatory Compliance...
Page 121: ...WAFER ULT3 ULT4 3 5 SBC Page 107 Appendix B B BIOS Options...
Page 124: ...WAFER ULT3 ULT4 3 5 SBC Page 110 Appendix C C Terminology...
Page 128: ...WAFER ULT3 ULT4 3 5 SBC Page 114 Appendix D D Digital I O Interface...
Page 131: ...WAFER ULT3 ULT4 3 5 SBC Page 117 Appendix E E Watchdog Timer...
Page 134: ...WAFER ULT3 ULT4 3 5 SBC Page 120 Appendix F F Hazardous Materials Disclosure...