IEI Technology PUZZLE-A001, User Manual

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PUZZLE-A001
Page 60
5.2.2 CPU Power Connector (CPU12V1)
Pin Description
1
2
3
4
1 GND
2 GND
3 +12 V
4 +12 V
Table 5-3: CPU Power Connector (CPU12V1) Pinouts
5.2.3 Chassis Intrusion Connector (CHASSIS1)
PIN NO. DESCRIPTION
1 +3.3VSB
2 CHASSIS OPEN
Table 5-4: Chassis Intrusion Connector (CHASSIS1) Pinouts
5.2.4 DIO Connector (DIO1)
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
10   9
 
 
 
2   1
1 GND 2 VCC
3 Output 3 4 Output 2
5 Output 1 6 Output 0
7 Input 3 8 Input 2
9 Input 1 10 Input 0
Table 5-5: DIO Connector (DIO1) Pinouts
5.2.5 EC Debug Connector (CN1)
PIN NO. DESCRIPTION PIN NO. DESCRIPTION
1 EC_EPP_STB# 2 EC_EPP_AFD#
3 EC_EPP_PD0 4 NC
5 EC_EPP_PD1 6 EC_EPP_INIT#
7 EC_EPP_PD2 8 EC_EPP_SLIN#