IEI Technology PCIE-9650, User Manual

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PCIE-9650 PICMG 1.3 CPU Card
Page 139
configuration option must be set to “ Manual ”) The following configuration options are
available
6 nanoseconds D
EFAULT
5 nanoseconds
4 nanoseconds
3 nanoseconds
DRAM RAS# to CAS# Delay [5 DRAM Clocks]
Use the DRAM RAS# to CAS# Delay option to specify the number of clock cycles must
elapse between sending a RAS (row address strobe) signal and the CAS (column address
strobe) signal. A pause is required between the RAS signal and the CAS signal to ensure
the memory is correctly addressed. (To be able to change this configuration option the
Configure DRAM Timing by SPD configuration option must be set to “ Disabled ”)
Configuration options are listed below:
2 DRAM Clocks
3 DRAM Clocks
4 DRAM Clocks
5 DRAM Clocks
6 DRAM Clocks D
EFAULT
DRAM RAS# Precharge [6 DRAM Clocks]
Use the DRAM RAS# Precharge option to set the speed at which the RAM terminates the
access of one row and start accessing another. (To be able to change this configuration
option the DRAM RAS# Precharge configuration option must be set to “ Manual ”) The
following configuration options are available
2 DRAM Clocks
3 DRAM Clocks
4 DRAM Clocks
5 DRAM Clocks
6 DRAM Clocks D
EFAULT