6. Signals and Pinout
154
Tsi310 User Manual
80B6020_MA001_05
6.3
Secondary Interface Signals
Table 14: Secondary Interface Signals
Signal Name
I/O
Width
Description
S_ACK64#
I/O
1
Acknowledge 64-Bit Transfer: Asserted by the currently addressed
target on the secondary bus to indicate its willingness to transfer data
using 64 bits.
S_AD(63:00)
I/O
64
Multiplexed Address and Data: These signals are the 64-bit
multiplexed address and data bus, shared by other devices on the
secondary bus. During a transaction, this bus contains the physical
bus address, attributes, or data, or it may be reserved.
S_C/BE(7:0)#
I/O
8
Multiplexed Bus Command and Byte Enables: During a transaction,
these eight bits define the bus command, attributes, or byte enables
for the transfer. These signals are shared with other agents on the
secondary bus and at times may be reserved.
S_CLK
I
1
Clock: Received by the bridge and provides timing for all operations
on the secondary interface.
S_DEVSEL#
I/O
1
Device Select: Asserted by the target on the secondary bus that
decoded the address of the current transaction as being within one of
its address ranges.
S_DEVSEL# is monitored by the bridge when performing a secondary
bus transaction on behalf of a primary bus master.
S_DEVSEL# is driven by the bridge when a secondary bus master is
performing a transaction on the secondary bus intended for a primary
bus slave.
S_FRAME#
I/O
1
Cycle Frame: Defines the beginning and duration of each secondary
bus transaction and is controlled by the initiator of the operation.
S_FRAME# is driven by the bridge when performing a secondary bus
transaction on behalf of a primary bus master.
S_FRAME# is monitored by the bridge when a secondary bus master
is performing a transaction on the secondary bus.
S_GNT1REQ#
O
1
Grant 1: This is a dual-purpose signal:
• When the Tsi310 internal arbiter is enabled this signal is used as a
grant output, and is activated by the bridge to grant the use of the
secondary bus to the master who requested the use with the
S_REQ1GNT# signal.
• When the Tsi310 internal arbiter is disabled, this signal is used by
the bridge as its request output signal.
S_GNT2# - S_GNT6#
O
5
Grants 2-6: Driven by the bridge's internal arbiter to grant usage of the
secondary bus to the master that activated the corresponding request
signal.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...